Backplane Testing System Using Differential Signal Transceiver
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Solution Overview
Problem
Traditional backplane testing methods are costly, limited in supporting high test frequencies, and unable to effectively test differential signal circuits with capacitors or redriver circuits, and they cannot test single lines or support high-speed serial interfaces.
Innovation Solution
A backplane testing system utilizing a loop device with dummy SAS units and a core testing device featuring a JTAG interface, differential signal transceiver, and control module that generates pseudo-random binary sequences and test signals conforming to the IEEE-1149.6 boundary scan standard to test differential signals, allowing for parallel control and high-speed testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional backplane testing method using server, hard disks and I/F card is adopted, then testing capability is provided, but test costs increase as number of interfaces increases
Solution Approach 1:
The patent merges multiple testing functions into a single integrated testing device. Instead of using separate servers, hard disks, and I/F cards for each interface, the invention consolidates these resources into one device that can test multiple SAS interfaces simultaneously, thereby reducing overall test costs while maintaining comprehensive testing capability.
Solution Approach 2:
The testing device is designed with multi-functionality to handle various SAS interface types and configurations. It can test different signal rates (6Gbps, 12Gbps, 24Gbps), support various backplane configurations, and perform multiple test types (functional testing, signal integrity testing) using a single unified platform, eliminating the need for multiple specialized testing systems.
2Ease of operation
If traditional I/F card is used for backplane testing, then testing is performed, but test frequency is limited and cannot support 2.5 Gbps or more
Solution Approach 1:
The patent implements parameter changes by designing the testing device with adjustable signal rate capabilities. The device can dynamically adapt its operating parameters to support different SAS signal rates including 6Gbps, 12Gbps, and 24Gbps, overcoming the fixed frequency limitations of traditional I/F cards through reconfigurable testing parameters.
3Ease of operation
If traditional backplane testing method is used, then testing is performed, but cannot test single line in differential signal circuit
Solution Approach 1:
The patent applies segmentation by enabling independent testing of individual lines within differential signal circuits. The testing device can isolate and test each signal line separately while maintaining the ability to perform combined differential pair testing, providing both granular single-line measurement precision and comprehensive multi-line testing capability.
4Ease of operation
If serial interfaces such as IIC and UART are used to control cascaded hard disks, then control is achieved, but test speed is slow
Solution Approach 1:
The patent replaces traditional serial communication interfaces (IIC, UART) with parallel communication architecture. The testing device uses parallel data buses and communication protocols to control multiple hard disks simultaneously, achieving significant speed improvements over sequential serial communication while maintaining full control functionality.
Data Source
AI summary
A backplane testing system is provided. Based on the connection relationship and signal transfer relationship of a differential signal transceiver, a backplane and a loop device, the differential signal transceiver generates a set of pseudo random binary sequence (PRBS) as a differential signal, and sends the differential signal and receives the returned differential signal, and then determines whether the differential signals sent and received are the same; and the differential signal transceiver generates a test signal that conforms to the IEEE-1149.6 boundary scan test standard, and sends the test signal and receives the returned test signal through a second positive differential signal circuit and a second negative differential signal circuit, and then determines whether the test signals sent and received through the second positive differential signal circuit are the same and whether the test signals sent and received through the second negative differential signal circuit are the same.