Flat Panel Display Backplane Reducing TFT Area via 3D Stacked Transistors

The patent transitions from conventional planar TFT structures to a 3D stacked configuration where multiple transistor layers are vertically integrated. This dimensional change allows transistors to be arranged in three dimensions rather than confined to a single plane, significantly reducing the footprint area while maintaining manufacturing feasibility through sequential layer formation processes

The patent implements nested transistor structures where smaller transistors are positioned within or adjacent to larger transistor regions in a hierarchical arrangement. This nesting approach allows multiple transistor functions to be compacted into overlapping or adjacent spatial zones, minimizing the total area occupied by the transistor array while preserving individual transistor functionality

The patent applies different structural optimizations to different transistor regions based on their functional requirements. Critical transistors handling high current or requiring high switching speed are given enhanced gate structures, larger channel widths, or optimized doping profiles, while less critical transistors use more compact designs. This localized quality adjustment maintains high transistor performance in key areas while achieving overall area reduction for high resolution

The patent employs composite material structures for transistor components, such as combining different semiconductor materials with complementary properties, using multi-layer gate dielectrics with optimized electrical characteristics, and integrating various conductive materials. These composite structures enable transistors to achieve superior electrical performance and reliability within reduced footprint dimensions through material property optimization rather than simply scaling down all dimensions