Backplane Time Synchronization With Timestamp Drift Correction
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Solution Overview
Problem
Industrial control systems face disruptions in time-sensitive network communications due to desynchronization in the PTP master time domain, leading to potential critical issues when sub-microsecond time precision is lost.
Innovation Solution
An industrial system with a microcontroller and two time modules, one generating a first timestamp and the other a second timestamp, calculates an offset and clock ratio to transmit a message correcting timestamps, ensuring sub-microsecond precision and maintaining internal PTP time decorrelated from fieldbus PTP time, allowing I/O modules to calculate absolute timestamps and maintain deterministic latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PTP time synchronization is used in industrial Ethernet networks, then time precision can be achieved, but desynchronization in the PTP master time domain causes communication disruptions
Solution Approach 1:
The patent introduces a timestamp correction mechanism that acts as an intermediary between the PTP time domain and the industrial Ethernet communication. The correction timestamp (ts_corr) mediates the time synchronization by compensating for drifts and desynchronization events, allowing precise timestamping without direct dependency on PTP master time stability.
Solution Approach 2:
The patent creates an asymmetric time domain architecture where the timestamp generation and correction mechanism operates independently from the PTP master time domain. The first time domain (local clock) and second time domain (PTP synchronized clock) are kept decorrelated, allowing the system to maintain precise timestamps even when PTP synchronization fails or drifts.
2Productivity
If all switches share a common time reference through PTP synchronization, then real-time communication with deterministic latency is enabled, but any desynchronization propagates to all underlying devices
Solution Approach 1:
The patent segments the time domain into multiple independent domains. Each switch and I/O module operates with its own local clock and timestamp correction mechanism, rather than relying on a single propagated PTP time reference. This segmentation prevents desynchronization in one domain from affecting others.
Solution Approach 2:
The patent implements prior cushioning by pre-calculating and applying timestamp corrections based on historical drift data and clock ratio measurements. The correction timestamp (ts_corr) is computed in advance using the formula ts_corr = ts1 - (ts2 - ts1) * cri, where cri is the clock ratio, cushioning against future desynchronization events before they propagate through the network.
3Measurement precision
If PTP time domain is used for TSN communications, then time synchronization is achieved, but critical issues occur when desynchronization happens in industrial environments
Solution Approach 1:
The correction timestamp mechanism serves as an intermediary layer between the PTP time domain and the application layer. It translates PTP timestamps into corrected timestamps that compensate for desynchronization, preventing critical issues while maintaining the benefits of PTP time synchronization.
Solution Approach 2:
The patent converts the harmful effect of PTP desynchronization into a beneficial correction mechanism. By measuring the drift between local clock and PTP-synchronized clock, and applying the correction formula ts_corr = ts1 - (ts2 - ts1) * cri, the system transforms potential communication failures into opportunities for enhanced timestamp accuracy through drift compensation.
Data Source
AI summary
An industrial system for controlling backplane communication, including: a microcontroller; a first time module belonging to a first time domain and generating a first timestamp at an event; and a second time module belonging to a second time domain and able to communicate with at least one Input/Output, I/O, module, generating a second timestamp at the event. The microcontroller, the first time module and the second time module are included in a control manager able to communicate with at least one Input/Output, I/O, module. The microcontroller is configured to: calculate an offset between the second timestamp and the first timestamp; compute a clock ratio between the second time domain and the first time domain; and transmit a message to the at least one I/O module, the message including the second timestamp, the offset and the clock ratio.