Backplane Transistor Doping for High Resolution Displays
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Solution Overview
Problem
Current display apparatus backplanes face challenges in achieving high resolution and reliability due to the short channel problem and increased off current, which deteriorates transistor performance, especially when channel widths are reduced to decrease pixel size.
Innovation Solution
The backplane design includes transistors with specific active layers, gate electrodes, and insulating layers, along with a storage capacitor, where low-density doped and halo doped areas are strategically formed to address the short channel issue, and a method of manufacturing that involves precise doping and layer formation to optimize transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If channel width is reduced to decrease pixel size, then display resolution is improved, but transistor performance deteriorates due to short channel problem and increased off current
Solution Approach 1:
The patent applies local quality by creating different doped regions (low-density doped area and halo doped area) with specific doping concentrations at different locations within the active layer. The low-density doped area is formed with a first doping concentration in a first region, while the halo doped area is formed with a second doping concentration in a second region adjacent to the gate electrode. This localized doping strategy allows optimization of transistor performance in specific areas without increasing overall channel width, thereby maintaining high display resolution while improving transistor reliability.
Solution Approach 2:
The patent employs parameter changes by varying the doping concentration parameters across different regions of the active layer. The low-density doped area uses a first doping concentration that is lower than the doping concentration in the source/drain regions, while the halo doped area uses a second doping concentration that is higher than the first but lower than the source/drain regions. This gradient doping approach modifies the electrical parameters locally to reduce off current and mitigate short channel effects, enabling transistors to maintain performance despite reduced channel dimensions for high-resolution displays.
2Area of stationary object
If channel width is reduced to decrease pixel size, then device area is reduced, but off current increases
Solution Approach 1:
The patent applies local quality by creating different doped regions (low-density doped area and halo doped area) with specific doping concentrations at different locations within the active layer. The low-density doped area is formed with a first doping concentration in a first region, while the halo doped area is formed with a second doping concentration in a second region adjacent to the gate electrode. This localized doping strategy allows optimization of transistor performance in specific areas without increasing overall channel width, thereby maintaining high display resolution while improving transistor reliability.
Solution Approach 2:
The patent employs parameter changes by varying the doping concentration parameters across different regions of the active layer. The low-density doped area uses a first doping concentration that is lower than the doping concentration in the source/drain regions, while the halo doped area uses a second doping concentration that is higher than the first but lower than the source/drain regions. This gradient doping approach modifies the electrical parameters locally to reduce off current and mitigate short channel effects, enabling transistors to maintain performance despite reduced channel dimensions for high-resolution displays.
Data Source
AI summary
A backplane for a display apparatus includes a substrate including a display area and a non-display area; a first transistor formed on the display area; and a second transistor formed on the non-display area, wherein a first active layer includes a first channel area, a first source area disposed on one side of the first channel area, a first drain area disposed on the other side of the first channel area, and a low-density doped area and a halo doped area that are adjacent to both ends of the first gate electrode, and the second active layer includes a second channel area, a second source area disposed on one side of the second channel area, and a second drain area disposed on the other side of the second channel area.