Backside Active Interconnects for Wafer-Scale Die Routing
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Solution Overview
Problem
Traditional semiconductor processing faces challenges in achieving high-density circuits with small features due to manufacturing constraints, leading to defective dies and inefficiencies in interconnect circuitry, particularly in achieving active switching between dies in full wafer devices.
Innovation Solution
Incorporating active interconnect layers with transistors on the backside of a full wafer device, allowing for active switching and improved signal routing between dies, which includes forming transistors in the global interconnect layers and using thin-film transistors over an interconnect layer, along with layer transfer of single-crystal material for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional semiconductor processing is used to scale features to smaller sizes, then increased density of functional units is achieved, but manufacturing constraints lead to defective dies and reduced reliability
Solution Approach 1:
The wafer is divided into multiple independently functional dies that can be tested and selected individually. Each die operates as an independent computational unit, allowing defective dies to be identified and excluded without affecting the functionality of other dies on the same wafer.
Solution Approach 2:
The patent changes the operational parameters by applying voltage to select only functional dies for active participation in computation. This electrical parameter control enables dynamic activation of reliable dies while excluding defective ones, thereby maintaining high system reliability despite manufacturing defects.
2Power
If multiple dies are interconnected to achieve wafer-scale integration, then computing power is enhanced, but interconnect circuitry becomes complex and signal transmission control becomes difficult
Solution Approach 1:
The interconnect circuitry is made dynamic through the use of selectable interconnect structures that can be activated or deactivated based on the functional status of dies. This dynamic configuration allows the system to adapt the interconnect topology to match the actual operational requirements, simplifying the effective complexity while maintaining high computing power.
Solution Approach 2:
The system performs self-configuration by automatically selecting functional dies and activating appropriate interconnect paths without external intervention. The interconnect circuitry self-adapts to the operational state of the dies, reducing the need for complex external control mechanisms.
3Ease of manufacture
If passive interconnect structures are used in full wafer devices, then manufacturing is simplified, but active switching between dies cannot be achieved
Solution Approach 1:
The interconnect structures are pre-configured during manufacturing with selective activation capability. While the physical interconnects are formed using simplified processes, they are designed with built-in selection mechanisms that enable active switching during operation, combining manufacturing simplicity with operational versatility.
Solution Approach 2:
The interconnect structures serve multiple functions: they provide both physical signal transmission pathways and active switching capability through voltage-controlled selection. This multi-functionality allows the same interconnect infrastructure to support both simplified manufacturing requirements and complex signal routing control.
4Productivity
If all dies on a wafer are utilized to maximize capacity, then productivity increases, but defective dies reduce overall reliability
Solution Approach 1:
The system dynamically adjusts the number of active computational units based on die functionality testing results. Functional dies are activated to maximize productive capacity, while defective dies are excluded from operation. This dynamic activation ensures that productivity is optimized based on the actual functional yield of the wafer.
Solution Approach 2:
The system incorporates feedback mechanisms through die functionality testing that inform the selection process. Test results provide feedback about which dies are functional, and this information is used to selectively activate only reliable dies for computational tasks, thereby maintaining high productivity with reliable operation.
Data Source
AI summary
Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.