Backside Interconnect Air Gaps for Lower IC Coupling Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) technology while maintaining performance and efficiency, particularly in reducing coupling capacitance and improving device speeds in complex circuit structures.
Innovation Solution
The introduction of air gaps in the backside interconnection structure of gate-all-around (GAA) transistors, which involves forming a conductive feature with a dielectric layer and a spacer structure, creates an air gap that isolates the conductive feature and reduces coupling capacitance, enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional interconnection structures are used in scaled-down ICs, then manufacturing complexity is reduced, but coupling capacitance increases and device speeds decrease
Solution Approach 1:
The patent introduces air gaps in the vertical dimension of the backside interconnection structure, creating three-dimensional spacing between conductive features. This vertical separation reduces coupling capacitance without increasing lateral footprint, enabling faster device operation while maintaining compact integration.
Solution Approach 2:
The patent applies air gap formation selectively at specific locations where coupling capacitance is most problematic, rather than uniformly throughout the entire interconnection structure. This localized approach reduces capacitance where needed while minimizing added structural complexity in other regions.
2Object-generated harmful factors
If air gaps are introduced in backside interconnection structure, then coupling capacitance is reduced and device speeds improve, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnection structure by introducing air gaps that divide continuous dielectric regions into separated zones. This segmentation creates electrical isolation between adjacent conductive features, reducing coupling capacitance while maintaining structural integrity through the spacer framework.
Solution Approach 2:
The patent uses spacer structures as intermediary elements that physically separate conductive features and define air gap regions. These spacers act as mediators that reduce capacitive coupling between adjacent interconnects while providing a framework for subsequent dielectric deposition and planarization processes.
3Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases and costs decrease, but coupling capacitance increases and device performance deteriorates
Solution Approach 1:
The patent addresses the capacitance issue arising from scaled-down geometries by utilizing the vertical dimension to create air gaps between conductive features. This three-dimensional approach maintains the high functional density achieved through scaling while reducing parasitic capacitance that would otherwise limit device performance.
Solution Approach 2:
The patent changes the physical parameters of the interconnection structure by introducing void spaces (air gaps) with different dielectric properties compared to conventional filled dielectric structures. This parameter change reduces the effective permittivity in critical regions, lowering coupling capacitance while maintaining the scaled-down geometry benefits for production efficiency.
Data Source
AI summary
A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.