Backside Air-Gap Semiconductor Layout for Low-Resistance Power Rails
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Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges in forming power rails and vias on the backside of ICs with reduced resistance and coupling capacitance, leading to increased voltage drop and power consumption as circuits scale down.
Innovation Solution
Incorporation of backside metal wiring layers with wider dimensions and backside air gaps to reduce power rail resistance and coupling capacitance, while using a bottom self-aligned capping layer for isolation between gate stacks and power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down along with the circuit, then device density increases, but voltage drop and power consumption increase
Solution Approach 1:
The patent introduces backside power rails that extend from the front surface through the substrate to the back surface, utilizing the third dimension (depth/substrate thickness) to create additional power distribution pathways. This dimensional transition allows power rails to bypass the planar scaling limitations, providing low-resistance paths that reduce voltage drop while maintaining high device density.
Solution Approach 2:
The power distribution system is segmented into front-side power rails, backside power rails, and interconnect structures. This segmentation allows each component to be optimized independently - front-side rails for local distribution, backside rails for long-distance low-resistance paths, and interconnects for vertical connectivity - thereby reducing overall power consumption while maintaining high density.
2Ease of manufacture
If conventional fabrication methods are used, then manufacturing process is simple, but coupling capacitance between power rails and gate stacks increases
Solution Approach 1:
The patent extracts the problematic coupling capacitance by removing dielectric material between the backside power rails and gate stacks to form air gaps. This extraction eliminates the harmful capacitive coupling while the remaining fabrication steps use conventional techniques, balancing manufacturing simplicity with reduced coupling capacitance.
Solution Approach 2:
The patent introduces air gaps (porous spaces) between power rails and gate stacks to reduce coupling capacitance. These air gaps serve as low-dielectric-constant regions that minimize capacitive coupling while maintaining structural integrity and allowing conventional fabrication processes to be used.
3Loss of energy
If air gaps are introduced to reduce coupling capacitance, then power consumption decreases, but fabrication complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the air gaps early in the fabrication process, before final interconnect formation. The dielectric material is selectively removed to create air gaps that then serve as isolation regions throughout subsequent processing steps, reducing coupling capacitance without requiring complex additional fabrication steps.
Solution Approach 2:
The patent uses a self-aligned capping layer as an intermediary structure that defines the air gap regions. This capping layer is formed conformally and then selectively removed to create air gaps, providing a simple intermediary mechanism that reduces coupling capacitance while maintaining fabrication simplicity through self-alignment.
Data Source
AI summary
A method includes forming a structure including a substrate, a sacrificial layer over the substrate, nanostructures stacked above the sacrificial layer, first and second source/drain (S/D) features sandwiching the nanostructures, and a gate structure wrapping around at least one of the nanostructures. The method further includes etching the substrate from the backside of the structure to form a backside trench exposing the first S/D feature, forming a backside S/D contact in the backside trench, recessing the sacrificial layer resulting in a portion of the backside S/D contact protruding from the sacrificial layer at the backside of the structure, depositing a seal layer under the backside S/D contact, and forming a backside interconnect layer under the seal layer. The seal layer caps an air gap between the gate structure and the seal layer.