Backside Airgap Interconnects for Low-Resistance IC Power Routing
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors below the 10 nanometer node is compounded by the trade-off between critical feature dimensions and spacing, leading to increased power network resistance and signal routing constraints, which affects performance and area efficiency in integrated circuits.
Innovation Solution
Implementing airgaps in the backside structure for power delivery and signal routing, allowing for wider pitches and reduced power network resistance, while eliminating the need for front-side power delivery networks, thus enabling free cell placement and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate and nanowire transistors are scaled below the 10 nanometer node, then device density and functional capacity are improved, but power network resistance and signal routing constraints increase
Solution Approach 1:
The patent implements backside power delivery and signal routing, transitioning from traditional planar front-side interconnects to a three-dimensional architecture where power and signal networks are established on the substrate backside. This dimensional shift allows independent optimization of front-side device density and back-side power distribution, resolving the trade-off between scaling devices and managing power network resistance.
Solution Approach 2:
The patent segments the interconnect functions by separating power delivery and signal routing into distinct backside networks. Airgaps are introduced to partition the backside substrate into isolated regions, enabling independent optimization of power delivery paths and signal routing paths. This segmentation reduces parasitic coupling and allows each network to be optimized independently for its specific function.
2Quantity of substance
If feature dimensions are reduced to increase device density, then capacity is improved, but spacing between features becomes constrained
Solution Approach 1:
By moving power delivery and signal routing to the backside substrate, the patent frees up front-side space, allowing reduced feature spacing without compromising interconnect functionality. The backside networks provide the necessary electrical connections without occupying lateral space on the front side where device density is maximized.
Solution Approach 2:
The backside substrate acts as an intermediary layer that provides power delivery and signal routing functionality without interfering with front-side device placement. This intermediate plane allows dense front-side patterning while maintaining adequate electrical connectivity through the substrate backside.
3Power
If traditional front-side power delivery networks are used, then power distribution is achieved, but cell placement flexibility is reduced
Solution Approach 1:
The patent implements backside power delivery networks that are spatially separated from the front-side device layer. This dimensional separation allows completely flexible cell placement on the front side, as power distribution pathways are established independently on the substrate backside, eliminating the need to reserve specific front-side routing corridors for power delivery.
4Loss of energy
If airgaps are introduced for backside signal routing, then power network resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent replaces traditional mechanical filling processes with self-aligned etching and sacrificial layer removal techniques to create airgaps. Instead of depositing and planarizing dielectric materials to fill interconnect spaces, the process uses selective etching to remove sacrificial materials, allowing air to naturally form the gap medium. This substitution simplifies the manufacturing steps while achieving the desired low-resistance power delivery paths.
Data Source
AI summary
Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.