Wraparound Backside Amorphous Layer for Low-Resistance Silicide Contacts

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The challenge in fabricating semiconductor devices lies in forming effective and reliable interconnect structures as the size of semiconductor devices decreases, particularly due to inefficient modification of epitaxial region surfaces, leading to high contact resistance.

Innovation Solution

An amorphous silicon-based layer is formed over the epitaxial region to enhance bonding with the silicide layer, using deposition techniques to ensure full wrapping of the backside surfaces, thereby reducing contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication processes are used to form interconnect structures, then manufacturing simplicity is maintained, but contact resistance remains high due to inefficient modification of epitaxial region surfaces

Engineering Contradiction:

Improvecontact resistanceVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

An amorphous silicon-based layer is formed over the epitaxial region before silicide layer formation. This preliminary amorphous layer modifies the epitaxial region surface in advance, creating a more reactive surface that enhances subsequent bonding with the silicide layer, thereby reducing contact resistance without requiring complex process changes

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The amorphous silicon-based layer acts as an intermediary between the epitaxial region and the silicide layer. This intermediate layer facilitates better bonding by providing a surface that is more reactive and compatible with the silicide material, effectively mediating the interface to reduce contact resistance

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If device size is reduced to continue scaling, then productivity and integration density improve, but forming effective interconnect structures becomes more difficult due to surface modification inefficiency

Engineering Contradiction:

Improveintegration densityVSAvoidinterconnect reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the physical and chemical parameters of the epitaxial region surface by forming an amorphous silicon-based layer. This layer has different properties than the crystalline epitaxial silicon, providing enhanced reactivity and bonding characteristics that enable reliable interconnect formation at smaller device dimensions where surface effects become more dominant

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces contact resistance by creating a reliable electrical interface between the epitaxial region and the silicide layer, improving the overall reliability of the semiconductor structure.

Implementation Method 1

An amorphous layer may be formed around a backside of the epitaxial region

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20250006807A1Semiconductor structure with wraparound backside amorphous layer

Publication Date: 2025.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.