Backside Antenna Feed Routing for Compact AiP RF Packages
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Solution Overview
Problem
Current antenna-in-package (AiP) semiconductor devices face challenges in reducing size and improving performance, particularly in high-frequency applications like millimeter wave frequencies, due to difficulties in routing the antenna feeding structure to effectively isolate and shield the feedline and antenna layer.
Innovation Solution
The proposed solution involves a semiconductor device with a radio frequency integrated circuit (RFIC) and antenna layers integrated into a fan-out wafer-level package, where the antenna feeding structure is routed along the backside of the semiconductor die, allowing for the placement of input/output connectors under the die, reducing the package size and providing a low signal loss solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the antenna feeding structure is routed on the front side of the semiconductor die, then the routing is simpler, but the isolation and shielding of the feedline and antenna layer is insufficient
Solution Approach 1:
The patent routes the antenna feeding structure through the backside of the semiconductor die instead of the front side, utilizing the third dimension (depth/thickness of the die) to achieve better isolation and shielding while maintaining routing feasibility. This dimensional change allows the feedline to be physically separated from other front-side components.
Solution Approach 2:
The antenna feeding structure is divided into multiple segments: a first portion on the front side, a second portion through the backside via via structures, and a third portion on the back side. This segmentation allows each portion to be optimized independently for its specific function and location.
2Volume of moving object
If the package size is reduced, then the integration density increases, but the space for routing and shielding structures is limited
Solution Approach 1:
By routing the antenna feeding structure through the backside of the die and utilizing vertical via structures, the patent effectively uses the depth dimension to accommodate routing and shielding elements without increasing the planar footprint, thus reducing overall package size while maintaining necessary structural complexity.
Solution Approach 2:
The antenna feeding structure is nested within the semiconductor die itself, using the die's internal volume and backside space to house routing and shielding elements. This nesting approach maximizes space utilization and reduces the external package dimensions.
3Loss of energy
If signal loss is reduced, then the RF performance improves, but the routing path becomes longer or more complex
Solution Approach 1:
The patent utilizes the backside routing path and vertical via structures to create a more direct signal path that avoids the congestion and interference present on the front side. This three-dimensional routing approach reduces signal loss by minimizing the interaction with other signal lines and reducing the effective electrical path length despite the physical complexity.
Data Source
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AI summary
A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.