Backside Bitline Contact Layout for High-Density DRAM TFTs
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Solution Overview
Problem
The challenge in integrated circuit design is to achieve higher memory cell density while maintaining transistor performance, particularly in dynamic random-access memory (DRAM) where space constraints due to capacitor reliability and interference between cells pose significant issues.
Innovation Solution
The implementation of a bit line contact (BLC) located on the underside or backside of a channel in a thin film transistor, allowing the bit line and storage node contact to be at different levels, which reduces spatial constraints and enables a longer gated channel length, thereby increasing memory cell density without compromising transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell architecture is used, then transistor performance is maintained, but memory cell density is limited due to space constraints
Solution Approach 1:
The patent applies dimensionality change by moving the bit line contact from the top surface to the backside/underside of the channel structure. This vertical repositioning creates additional spatial freedom in the horizontal plane, allowing for reduced cell area and increased memory cell density without compromising transistor performance
2Length of moving object
If bit line contact is located on top of channel, then manufacturing is simplified, but gated channel length is constrained
Solution Approach 1:
The patent inverts the conventional contact configuration by placing the bit line contact on the backside/underside of the channel rather than on the top surface. This inversion enables longer gated channel lengths to be achieved while managing the increased structural complexity through careful design of the contact architecture
Data Source
AI summary
An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.