Backside Illuminated Bonding Pad Structure for CMOS Image Sensors
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Solution Overview
Problem
CMOS image sensors face reduced sensitivity due to obstacles in the pixel area from metallization and polysilicon features, which can be mitigated by backside illumination, but existing methods struggle with bonding quality and substrate thinning for effective photon collection.
Innovation Solution
A semiconductor device with a bonding pad is developed, featuring a substrate with semiconductor elements, inter-metal dielectric layers, and a conductive pattern exposed through the substrate for improved bonding and illumination, using techniques like damascene processing and wire bonding to enhance adhesion and prevent peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the substrate is thinned to enable backside illumination, then photon collection efficiency is improved, but bonding quality deteriorates due to reduced structural support
Solution Approach 1:
A bonding pad structure is formed on the front surface of the substrate before thinning the substrate. This bonding pad includes a lowermost metal pattern in the first inter-metal dielectric layer, which is exposed through an opening after substrate thinning. The bonding pad is prepared in advance to ensure proper bonding even when the substrate is thinned to enable backside illumination.
Solution Approach 2:
The bonding pad structure extends across multiple layers and dimensions: the lowermost metal pattern is disposed in the first inter-metal dielectric layer, and an opening through the substrate exposes this metal pattern from the backside. This multi-dimensional structure provides both mechanical support for bonding and enables backside illumination through the thinned substrate.
2Adaptability or versatility
If metallization and polysilicon features are added to the pixel area, then device functionality is improved, but sensitivity deteriorates due to photon blocking
Solution Approach 1:
The substrate is divided into distinct functional areas: a device area containing semiconductor elements with metallization and polysilicon features, and a bonding area with the bonding pad structure. This segmentation allows different regions to serve different functions - the device area provides functionality while the bonding area enables backside illumination and wire bonding.
Solution Approach 2:
Instead of illuminating from the front side where metallization and polysilicon block photons, the substrate is thinned and illuminated from the backside. The bonding pad structure is configured so that the lowermost metal pattern is exposed through an opening from the backside, allowing photons to reach the sensitive area without being blocked by front-side metallization.
3Ease of manufacture
If the bonding pad is exposed through the substrate, then wire bonding is improved, but structural integrity deteriorates
Solution Approach 1:
The bonding pad structure including the lowermost metal pattern in the first inter-metal dielectric layer is formed before substrate thinning. This preliminary formation ensures that the bonding pad has proper adhesion and structural characteristics before the substrate is thinned, maintaining both bondability and structural integrity.
Solution Approach 2:
The bonding pad structure comprises multiple materials: the lowermost metal pattern (conductive material), the first inter-metal dielectric layer (insulating material), and the substrate material. This composite structure provides both the electrical conductivity needed for wire bonding and the mechanical strength needed for structural integrity, even when the substrate is thinned.
Data Source
AI summary
A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern.