Backside Boost Capacitor Layout for Dense SRAM Write Assist
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Solution Overview
Problem
Existing SRAM devices with negative boosting techniques face challenges in maintaining capacitive value and real estate utilization due to the shrinking size of transistors, leading to suboptimal write performance and increased risk of device failures.
Innovation Solution
A negative voltage generator is implemented with a boost capacitor having a majority portion formed on the backside of the substrate, allowing for increased capacitive value and efficient use of frontside real estate by forming backside conductive lines as boost capacitors, which can be thicker and thus offer higher surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of transistors is shrunk to increase memory density, then the capacitive value of the boost capacitor decreases, but the real estate utilization improves
Solution Approach 1:
The patent moves the boost capacitor from the frontside to the backside of the substrate, utilizing the third dimension (vertical stacking) to resolve the contradiction. This allows the capacitor to maintain larger physical dimensions and higher capacitive value while the frontside transistors continue to shrink for increased memory density.
Solution Approach 2:
The substrate is divided into frontside and backside functional regions. The frontside contains the memory array with shrunk transistors for high density, while the backside houses the boost capacitor with larger dimensions for adequate capacitive value, allowing both requirements to be satisfied simultaneously.
2Ease of manufacture
If the boost capacitor is formed on the frontside with standard thickness, then the manufacturing process is simple, but the capacitive value is insufficient for adequate write performance
Solution Approach 1:
By relocating the capacitor to the backside, the patent enables the use of thicker conductive lines and larger surface area without complicating the frontside manufacturing process. The backside can be processed independently with optimized thickness parameters to achieve adequate capacitive value for write performance.
3Reliability
If the conductive lines are made thicker to increase capacitive value, then the capacitive value increases, but the available layout area decreases
Solution Approach 1:
The patent resolves this area-thickness tradeoff by moving the capacitor to the backside of the substrate. This vertical separation allows the conductive lines to be made thicker on the backside without consuming any additional footprint area on the frontside layout, thereby increasing capacitive value while maintaining layout efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances write performance by increasing the capacitive value of the boost capacitor by 16-25% within the same layout area, reducing discharge time and improving read operations efficiency.
Implementation Method 1
a first capacitor having a first terminal and a second terminal electrically coupled to a drain and a gate of the transistor, respectively
Data Source
AI summary
A device includes a memory array formed on a front side of a substrate. The memory array is accessible through a plurality of bit lines. The memory device includes a switch transistor formed on the front side of the substrate. The switch transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on a back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines, in response to the switch transistor being turned off.