Backside Boost Capacitor for SRAM Write Performance
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Solution Overview
Problem
Existing SRAM devices with negative boosting face challenges in maintaining capacitive value and real estate usage due to the shrinking size of transistors and the conventional placement of boost capacitors on the frontside of the substrate.
Innovation Solution
The SRAM device incorporates a negative voltage generator with a boost capacitor, where at least a majority portion of the boost capacitor is formed on the backside of the substrate, allowing for increased capacitive value and efficient use of frontside real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the boost capacitor is placed on the frontside of the substrate, then the device structure is simplified and manufacturing is easier, but the capacitive value is reduced and frontside real estate is wasted
Solution Approach 1:
The patent moves the boost capacitor from the frontside (2D plane) to the backside of the substrate, utilizing the third dimension (depth/thickness) and the previously unused backside area. This dimensional transition allows the capacitor to achieve larger capacitive value (16-25% improvement) without interfering with frontside circuitry, effectively resolving the contradiction between ease of manufacture and capacitive value.
2Device complexity
If the boost capacitor is placed on the frontside of the substrate, then the device structure is simplified, but the frontside real estate usage is reduced
Solution Approach 1:
By relocating the boost capacitor to the backside of the substrate, the patent utilizes the previously underutilized backside area, thereby increasing the effective area available for capacitor placement without adding complexity to the frontside device structure. This resolves the contradiction between device complexity and frontside real estate usage.
3Quantity of substance
If the boost capacitor size is increased to maintain capacitive value, then the capacitive value is improved, but the discharge time increases
Solution Approach 1:
The patent changes the physical parameters of the boost capacitor by relocating it to the backside of the substrate, where it can achieve larger capacitive value (16-25% improvement) without proportionally increasing discharge time. The backside placement allows for optimized capacitor geometry and closer proximity to the bit line, improving the charge-discharge efficiency and resolving the contradiction between capacitive value and discharge time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the capacitive value of the boost capacitor by 16-25% compared to conventional designs, improving write performance and reducing discharge time, thereby facilitating faster and more efficient read operations.
Implementation Method 1
a first capacitor having a first terminal and a second terminal electrically coupled to a drain and a gate of the transistor, respectively
Data Source
AI summary
A device includes a memory array formed on a front side of a substrate. The memory array is accessible through a plurality of bit lines. The memory device includes a switch transistor formed on the front side of the substrate. The switch transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on a back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines, in response to the switch transistor being turned off.