Backside Power Rail Integration With Local Interconnect for Low-Delay Cells
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Solution Overview
Problem
Current semiconductor device designs lack integration of backside power rails and power distribution networks with local interconnects, leading to high resistance bottlenecks and circuit delay issues due to tight metal pitches and smaller vias.
Innovation Solution
The integration of backside power rails between N channel and P channel field effect transistor spaces, along with backside local signal lines between these power rails, forms a semiconductor device that reduces resistance by utilizing backside metal in a standard cell architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tight metal pitches and smaller vias are used to increase integration density, then device integration is improved, but resistance increases causing performance degradation
Solution Approach 1:
The patent introduces backside power rails and signal lines on the opposite side of the substrate from the frontside metal interconnects. This adds a new dimensional layer (backside vs. frontside) for power distribution and signaling, allowing current to flow through shorter paths with lower resistance while maintaining high integration density on the frontside.
Solution Approach 2:
The power distribution network is segmented into frontside metal interconnects for high-density routing and backside power rails for low-resistance power delivery. This segmentation allows each layer to optimize for its specific function: the frontside for integration density and the backside for electrical performance.
2Area of stationary object
If backside power rails are positioned between N channel and P channel transistors, then space utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The backside power rails are merged with the substrate structure itself, utilizing the same fabrication processes that create the transistors and other device features. This integration approach combines power delivery functionality with the existing device architecture without requiring separate manufacturing steps.
Solution Approach 2:
The backside power rails are strategically positioned in specific locations between N channel and P channel transistors where space is available and electrical performance is most beneficial. This localized placement optimizes space utilization while maintaining manufacturing feasibility through targeted structuring in high-value regions.
Data Source
AI summary
A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.