3D SoIC Backside Bridge Interconnects for Low-Latency Chiplets
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Solution Overview
Problem
Conventional through-silicon vias in integrated circuit packaging are inefficient for high power-efficiency and low latency requirements due to long wiring paths.
Innovation Solution
Formation of backside bridge structures on a first-tier chip with electrical paths between second-tier chips, utilizing damascene processes to create short electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias are used for interchip communication, then electrical connections between chips are established, but wiring paths become long resulting in high latency and low power efficiency
Solution Approach 1:
The patent transitions from conventional planar wiring to three-dimensional vertical interconnections using through-silicon vias and stacked chip architecture. This dimensional change enables direct vertical pathways between chips, dramatically shortening signal paths and reducing latency while maintaining connection reliability through precise vias alignment and bonding interfaces.
2Reliability
If through-silicon vias are used for interchip communication, then electrical connections between chips are established, but power efficiency deteriorates due to long wiring paths
Solution Approach 1:
By implementing vertical through-silicon via connections and stacking chips in three dimensions, the patent creates direct short pathways that minimize signal transmission distance. This dimensional transition reduces resistive losses and parasitic effects, thereby improving power efficiency while maintaining robust electrical connections between chips.
3Ease of manufacture
If conventional interconnect structures are used, then chip bonding is simplified, but signal path length increases reducing performance
Solution Approach 1:
The patent employs preliminary formation of through-silicon vias, conductive plugs, and interconnect structures within each chip before the bonding process. This advance preparation enables direct vertical connections upon stacking, eliminating the need for complex post-bonding routing while achieving short signal paths and high transmission speeds.
Data Source
AI summary
A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.