Backside Buried Contact Layout for Low-Resistance SRAM Interconnects
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Solution Overview
Problem
Conventional SRAM devices face challenges with increased parasitic resistance, capacitance, and poor connection due to densely spaced metal lines and gate vias, leading to performance degradation and manufacturing complexity.
Innovation Solution
The introduction of a backside buried contact that extends through the semiconductor device to directly connect the gate stack and source/drain feature, reducing frontside via density and allowing for wider metal lines, thereby improving connectivity and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metal lines are reduced in dimension to accommodate densely spaced transistors, then device integration density is improved, but parasitic resistance increases and connection quality deteriorates
Solution Approach 1:
The patent introduces a vertical dimension by forming backside buried contacts that extend through the substrate thickness. This allows electrical connections to be established from the backside of the device, adding a third dimension to the interconnect architecture. The backside buried contact extends from the backside surface through the substrate to contact the channel layer, enabling power and signal distribution without constraining the frontside metal line dimensions.
Solution Approach 2:
The patent segments the interconnect function into multiple independent pathways: frontside metal lines for signal routing and backside buried contacts for power distribution and additional signaling. This segmentation allows each interconnect layer to be optimized independently, with the backside contacts providing redundant or alternative pathways that reduce the burden on frontside metal lines.
2Quantity of substance
If metal lines are reduced in dimension to accommodate densely spaced transistors, then device integration density is improved, but parasitic capacitance increases
Solution Approach 1:
By moving power distribution to the backside buried contacts, the patent separates power routing from signal routing in the vertical dimension. This reduces the capacitance burden on frontside metal lines, as the backside contacts provide dedicated power pathways that are electrically isolated from the signal-carrying metal lines on the frontside.
3Length of moving object
If frontside via density is reduced to improve metal line width, then metal line resistance decreases, but device connectivity may be compromised
Solution Approach 1:
The backside buried contact provides an alternative connectivity pathway that compensates for reduced frontside via density. By establishing connections through the backside of the substrate, the patent creates redundant routing paths that maintain device connectivity even when frontside via density is reduced to allow wider metal lines.
4Ease of manufacture
If conventional frontside-only contact architecture is used, then manufacturing process is simple, but metal line dimensions are constrained leading to increased parasitic resistance
Solution Approach 1:
The patent extends the contact architecture into the vertical dimension by forming backside buried contacts. This is achieved by: (1) forming a trench from the backside surface to expose the channel layer, (2) depositing a conductive material in the trench, and (3) planarizing the backside surface. This additional vertical dimension provides enhanced electrical connections without fundamentally altering the conventional planar fabrication workflow.
Data Source
AI summary
A semiconductor structure includes an active region including a stack of channel layers, a metal gate structure disposed over the stack of channel layers, a source/drain feature disposed over a source/drain region of the active region and adjacent to the stack of channel layers, and a backside via penetrating from a back side of the active region and extending to contact a channel layer of the stack of channel layers. The backside via is electrically connected to the source/drain feature through the channel layer of the stack of channel layers and contacts the metal gate structure.