Backside Buried Interconnect Layout for Buried Power Rail Scaling

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Solution Overview

Problem

Current methods for forming buried power rails (BPRs) in semiconductor devices face challenges such as high-aspect-ratio etching complexities and space constraints, which hinder the scaling of device pitches and efficient power delivery.

Innovation Solution

A method involving the formation of a trench beneath the source/drain region, with a dielectric liner and a dummy interconnect, allowing for backside connection of buried interconnects, which reduces space requirements and enables wider interconnects without increasing device pitch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If frontside processing is used to form Via-to-BPR connections, then power delivery to buried power rails is achieved, but device pitch scaling is hindered due to space requirements and high-aspect-ratio etching complexities

Engineering Contradiction:
Improvepower deliveryVSAvoiddevice pitch
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent inverts the conventional approach by forming the buried power rail connection from the backside of the substrate rather than from the frontside. This is achieved by etching through the substrate from the backside to contact the BPR, thereby eliminating the need for high-aspect-ratio frontside etching and reducing space requirements on the frontside interconnect structure.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If Via-to-BPR connections are formed on the frontside, then power delivery is enabled, but frontside interconnect congestion increases and routing resources are consumed

Engineering Contradiction:
Improvepower deliveryVSAvoidfrontside interconnect structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent moves the power delivery connection from the frontside (2D plane) to the backside of the substrate, utilizing the third dimension (depth/vertical direction) to resolve the congestion issue. By forming the connection through the substrate thickness from the backside, the frontside interconnect structure is freed from power delivery routing requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If high-aspect-ratio etching is used for Via-to-BPR formation, then frontside connection is achieved, but process complexity and manufacturing challenges increase

Engineering Contradiction:
Improveconnection formationVSAvoidetching process
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent inverts the etching direction by performing the etch from the backside of the substrate rather than the frontside. This approach creates a shallower etch profile with lower aspect ratio, as the etch terminates at the BPR interface without needing to traverse the full depth from the frontside contact level, thereby simplifying the manufacturing process.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach facilitates efficient power delivery and signal routing by allowing backside contacting of buried interconnects, reducing frontside congestion and enabling more flexible design for buried interconnects, thus improving semiconductor device performance.

Implementation Method 1

forming a dielectric liner on interior surfaces of the trench

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 2

removing the dummy interconnect selectively to the dielectric liner

Methodology Applied
Scientific EffectEtching: Ablation

Data Source

PatentUS20240178051A1Method for Forming a Semiconductor Device
Publication Date: 2024.05.30 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US20240178051A1 patent drawing
  • US20240178051A1 patent drawing
  • US20240178051A1 patent drawing

AI summary

A method includes: forming a structure on a frontside of a substrate, the structure including a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body including a channel layer extending between the first and second source/drain bodies; forming a trench beside the first source/drain region by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a liner on the trench; forming an opening in the liner underneath the first source/drain region; and forming a dummy interconnect in the trench; where the method further includes exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the liner; and forming a buried interconnect of a conductive material in the trench, where the buried interconnect is connected to the first source/drain body via the opening in the liner.