Backside Decoupling Capacitor Layout for Low PDN Impedance
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Solution Overview
Problem
Integrated circuits face challenges in reducing power delivery network impedance due to limited space for large decoupling capacitors, which are necessary to mitigate power supply voltage fluctuations and noise, especially in high-power and high-frequency applications.
Innovation Solution
A backside decoupling capacitor is integrated into the die, utilizing the backside region to provide a large decoupling capacitance with interdigitated metal traces and through-silicon vias to enhance proximity and capacitance, reducing power delivery network impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large decoupling capacitors are provided to reduce power delivery network impedance, then power supply voltage fluctuations are mitigated, but relatively large portions of the die are required
Solution Approach 1:
The patent moves the decoupling capacitor from the traditional planar location on the front side of the die to the back side of the die, utilizing the third dimension (vertical depth) and the underutilized backside area. This dimensional transition allows the capacitor to be positioned closer to the power delivery network without consuming additional lateral die area, thereby resolving the contradiction between providing sufficient capacitance and preserving die area.
Solution Approach 2:
The decoupling capacitor is integrated within the existing backside region of the die structure, nesting it into the available space that would otherwise be unused or used for packaging. The capacitor structure is embedded within the die's vertical architecture, utilizing the depth dimension and backside metal layers to house the capacitor without adding to the die's footprint.
2Object-affected harmful factors
If decoupling capacitance is increased to reduce power delivery network impedance, then noise impact is reduced, but device complexity increases
Solution Approach 1:
The backside metal layers and through-silicon vias are designed to serve multiple functions: they provide electrical connections for the power delivery network while simultaneously forming the electrodes and interconnections for the decoupling capacitor. This multi-functionality reduces the need for separate capacitor structures and interconnects, thereby reducing overall device complexity while still providing the necessary noise reduction.
Solution Approach 2:
The patent merges the power delivery network infrastructure with the decoupling capacitor structure by using the same backside metal traces and through-silicon vias for both power distribution and capacitor interconnections. This consolidation eliminates redundant structures and simplifies the overall device architecture while achieving effective noise reduction through the integrated capacitor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The backside capacitor effectively reduces power delivery network impedance, improving the performance and reliability of integrated circuits by providing close proximity and increased capacitance, thus supporting high-power and high-frequency applications.
Implementation Method 1
Capacitors can be used to provide decoupling capacitances that reduce power delivery network impedance
Implementation Method 2
A dielectric material is arranged between the at least two respective portions of the backside metal traces
Data Source
AI summary
A die has an integrated circuit with backside decoupling capacitance that reduces impact of noise caused by a power delivery network supplying power to the integrated circuit. The integrated circuit includes a power delivery network spanning a front end of line region, a back end of line region, and a backside region. The integrated circuit includes a decoupling capacitor disposed in the backside region to provide a backside decoupling capacitance. The decoupling capacitor includes at least two respective portions of at least two of backside metal traces such that each of the at least two respective portions are electrically coupled to at least one of the front end of line region or the back end of line region by at least two respective through-silicon vias among the plurality of through-silicon vias, and a dielectric material is arranged between the at least two respective portions of the backside metal traces.