Back-Side High-Q Capacitors Using Through-Wafer Interconnects
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Solution Overview
Problem
Conventional semiconductor IC chip designs face challenges in achieving high-Q on-chip capacitors due to limited 2D/3D silicon space, leading to reduced integration density and performance, as existing capacitor technologies either result in poor performance at high integration densities or consume valuable silicon real estate.
Innovation Solution
The fabrication of high-Q on-chip capacitors on the chip back-side connected to integrated circuits on the chip front-side using through-wafer embedded interconnects, specifically utilizing a SOI substrate with buried insulating layers and metallic plugs to form stacked capacitor structures, allowing for high-quality capacitors with minimal parasitic impedances and preserved front-side silicon real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional on-chip capacitor technologies are used to achieve high integration density, then integration density is improved, but capacitor quality factor (Q) deteriorates due to increased parasitic impedances
Solution Approach 1:
The patent moves capacitor fabrication from the traditional front-side 2D plane to the back-side of the wafer, utilizing the third dimension (depth/vertical space) and the previously underutilized back-side surface. This dimensional transition allows capacitors to be formed in a separate domain, avoiding the parasitic impedance issues that arise from high-density front-side integration while maintaining high capacitance density through vertical stacking structures.
Solution Approach 2:
The wafer is segmented into front-side and back-side functional regions, with through-wafer interconnects acting as separation boundaries. This segmentation allows independent optimization of front-side circuitry and back-side capacitor structures, enabling high-Q capacitors to be formed without compromising front-side integration density or introducing parasitic effects from adjacent capacitor structures.
2Quantity of substance
If front-side silicon real estate is used for capacitor fabrication, then capacitor integration is achieved, but available area for high-density circuit integration is reduced
Solution Approach 1:
The patent utilizes the back-side of the wafer, an previously underutilized dimension, for capacitor fabrication. This allows capacitors to be integrated without consuming front-side silicon real estate, effectively doubling the available fabrication space and enabling both high-density circuit integration on the front-side and high-capacitance-density integration on the back-side.
Solution Approach 2:
Capacitors are formed as stacked structures that nest within the vertical space of the wafer thickness, utilizing the bulk silicon layer between the back-side surface and the front-side circuitry. This nested configuration allows high capacitance values to be achieved within the existing wafer footprint without requiring additional lateral space.
3Quantity of substance
If deep-trench or stacked capacitor techniques are used to achieve high capacitance density, then capacitance density is improved, but dielectric integrity deteriorates due to thin dielectric layers susceptible to breakdown
Solution Approach 1:
The patent changes the physical parameters of the capacitor structure by forming capacitors in the bulk silicon layer with through-wafer interconnects, allowing for thicker effective dielectric paths while maintaining high capacitance density. The stacked configuration with metal plates and dielectric layers creates a geometry that sustains higher voltage stress without breakdown, unlike thin sidewall dielectric layers in deep-trench capacitors.
4Volume of stationary object
If on-chip capacitors are used instead of discrete off-chip components, then chip package size and cost are reduced, but parasitic impedances increase
Solution Approach 1:
By relocating capacitors to the back-side of the wafer and using through-wafer interconnects, the patent minimizes the interconnect path length between capacitors and circuits. This dimensional reconfiguration reduces the area occupied by interconnect traces and associated parasitic inductances and resistances, allowing on-chip capacitors to achieve performance comparable to or better than discrete off-chip components.
Data Source
AI summary
Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.