Backside Decoupling Capacitor Layout for TSV Power Distribution
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges with introducing power signal routing on the wafer backside due to potential interference with backside circuit elements, processing difficulties with through silicon via (TSV) interconnects, and compatibility issues with wafer front-end-of-line (FEOL) and back-end-of-line (BEOL) fabrication, leading to resistance, capacitance, and power consumption problems.
Innovation Solution
The integration of backside power and ground distribution conductors with through silicon via (TSV) structures and decoupling capacitors, formed after substantial FEOL and BEOL processing, to maximize power and ground distribution while providing EMI shielding, using selective etching and electroplating processes to create separate connections with decoupling capacitor plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power signal routing is introduced on the wafer backside, then power delivery efficiency is improved, but interference with backside circuit elements occurs
Solution Approach 1:
The patent segments the backside of the wafer into distinct regions: one for power signal routing and another for decoupling capacitor placement. This spatial segmentation allows power delivery pathways to be separated from sensitive circuit elements, reducing electromagnetic interference while maintaining high power delivery efficiency through dedicated routing paths.
2Reliability
If through silicon via (TSV) interconnects are created, then direct electrical connection is improved, but processing difficulty increases
Solution Approach 1:
The patent performs preliminary actions by forming the TSV interconnect structures and establishing electrical connections to the decoupling capacitor plates before finalizing the backside circuit element fabrication. This preliminary establishment of reliable electrical pathways allows subsequent processing steps to proceed without compromising connection integrity, thereby improving manufacturability while maintaining connection reliability.
3Device complexity
If power wiring is moved to the wafer backside, then frontside metallization congestion is reduced, but process compatibility challenges arise
Solution Approach 1:
The patent moves power wiring from the traditional two-dimensional frontside metallization plane to the three-dimensional backside of the wafer. This dimensional transition relocates power distribution pathways to an unused spatial dimension, eliminating congestion on the frontside while the process compatibility challenges are addressed through carefully sequenced fabrication steps that integrate backside processing with front-end-of-line and back-end-of-line operations.
4Object-affected harmful factors
If decoupling capacitor plates are formed on the backside, then EMI shielding is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of decoupling capacitor plates with the power and ground distribution network fabrication process. By combining these functions into a unified manufacturing sequence where capacitor plates are formed as integral parts of the backside power distribution structure, the EMI shielding benefit is achieved while the manufacturing complexity is reduced through process integration rather than separate fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces front-side metallization congestion, resistance, and power consumption, while improving EMI shielding and addressing compatibility issues, enhancing the efficiency of power and ground signal routing through the substrate backside.
Implementation Method 1
using selective etching and electroplating processes to create separate connections with decoupling capacitor plates
Data Source
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AI summary
A backside power and ground distribution network is formed on an semiconductor wafer having a decoupling capacitor on a backside of the semiconductor substrate layer by selectively etching a TSV openings through the decoupling capacitor and the backside of the semiconductor substrate layer to contact integrated device connection features and then forming, in the TSV openings, a ground TSV conductor which provides a direct electrical connection between the first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer and also forming a power TSV conductor which provides a direct electrical connection between the second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer, where the ground TSV conductor is not directly, electrically connected to the second capacitor plate, and where the power TSV conductor is not directly, electrically connected to the first capacitor plate.