Backside Power Rail Cell Architecture for Shorter Signal Paths
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Solution Overview
Problem
Long signal routing paths in semiconductor cell architectures lead to signal attenuation, delay, and interference, making device performance and manufacturing complex, due to the fixed positions of frontside power rails and metal lines.
Innovation Solution
The introduction of a backside power distribution network (BSPDN) with backside power rails and metal lines that are flexibly positioned, allowing for reduced signal routing lengths and minimized interference by overlapping with cell boundaries and metal lines in a way that optimizes cell placement and reduces the semiconductor device's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If frontside power rails and metal lines are used with fixed positions, then cell architecture is simplified, but signal routing paths become long causing signal attenuation, delay, and interference
Solution Approach 1:
The patent introduces backside power rails that extend in the cell-length direction and vertically overlap with cell inside areas, utilizing the vertical dimension (z-axis) to create a three-dimensional power distribution network. This allows power delivery from the backside of the substrate, enabling shorter signal routing paths on the frontside by reducing the need for long horizontal power delivery paths, thereby decreasing signal attenuation, delay, and interference while maintaining architectural simplicity.
2Ease of operation
If backside power rails are positioned to vertically overlap cell inside areas, then signal routing paths are shortened, but manufacturing precision requirements increase
Solution Approach 1:
The backside power rails are segmented into multiple discrete rails extending in the cell-length direction at predetermined pitches, rather than forming a single continuous structure. This segmentation allows for modular manufacturing and placement, reducing the cumulative precision requirements compared to a single long rail. Each segment can be manufactured and positioned independently, making the overall system more tolerant to manufacturing variations while still achieving short signal routing paths.
3Area of stationary object
If cells are arranged with full side boundary sharing, then device footprint is minimized, but signal interference and short circuit risk increase
Solution Approach 1:
The backside power rails serve as an intermediary power delivery structure that is positioned to vertically overlap with cell inside areas rather than cell boundaries. This intermediary positioning allows adjacent cells to share full side boundaries for area efficiency, while the backside power rails provide electrical isolation and dedicated power paths that prevent signal interference and short circuit risks between adjacent cells, effectively decoupling the area optimization from the interference problem.
Data Source
AI summary
Provided is a semiconductor cell architecture which includes a plurality of cells, a plurality of backside power rails, and a plurality of metal lines, wherein the backside power rails are extended in a cell-length direction, and at least one backside power rail vertically overlaps an inside area of at least one cell without vertically overlapping a lower boundary or an upper boundary of the at least one cell in a plan view.