Backside Clamp Circuit for Area-Efficient Bidirectional ESD Protection
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Solution Overview
Problem
Miniaturized integrated circuits are susceptible to electrostatic discharge (ESD) events due to thinner dielectric thicknesses and lowered dielectric breakdown voltages, leading to potential electronic circuit damage.
Innovation Solution
Incorporation of a clamp circuit with a first transistor and a charging circuit to detect and discharge ESD current in both forward and reverse directions, utilizing a channel of the clamp circuit to efficiently manage ESD events, thereby reducing damage while occupying less area compared to traditional body diode approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional body diode approaches are used for ESD protection, then ESD discharge capability is provided, but occupied area is excessive
Solution Approach 1:
The ESD protection function is segmented into multiple specialized circuits: a clamp circuit for forward ESD discharge, a mirror circuit for reverse ESD discharge, and a detection circuit for triggering. This segmentation allows each circuit to be optimized for its specific function with minimal area, replacing the large traditional body diode approach.
Solution Approach 2:
The patent utilizes the third dimension by stacking circuits vertically in layers. The clamp circuit, mirror circuit, and detection circuit are arranged in different layers, allowing high-density integration and reducing the planar footprint area occupied by the ESD protection circuitry.
2Productivity
If miniaturization is pursued to reduce device size, then power consumption decreases and functionality increases, but susceptibility to ESD events increases
Solution Approach 1:
The detection circuit continuously monitors for ESD events and triggers the clamp and mirror circuits in advance before damage occurs. The low threshold voltage design ensures early detection and activation of protection mechanisms, counteracting the increased ESD susceptibility caused by miniaturization.
Solution Approach 2:
The patent introduces low threshold voltage transistors as intermediary elements that are highly sensitive to ESD events. These transistors act as early warning sensors that trigger the protection circuits before the ESD damage propagates through the miniaturized circuitry.
3Reliability
If ESD protection circuit is added to protect against electrostatic discharge, then circuit damage is prevented, but device complexity increases
Solution Approach 1:
The clamp circuit and mirror circuit share common components and are controlled by the same detection circuit, allowing a single ESD event detection mechanism to protect against both forward and reverse ESD polarity events. This multi-functionality reduces overall circuit complexity compared to having separate protection circuits for each ESD direction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances ESD discharging capability and performance while minimizing the occupied area, providing effective protection against ESD events in integrated circuits.
Implementation Method 1
electrostatic discharge (ESD) events due to various factors, such as thinner dielectric thicknesses and associated lowered dielectric breakdown voltages
Data Source
AI summary
A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first and second node, a discharging circuit coupled between the first and second node, a charging circuit, and a first conductive structure on the back-side of the semiconductor wafer, and extending into the first well and being directly coupled to the first source of the first transistor. The discharging circuit includes a first transistor of a first type in a semiconductor wafer. The first transistor includes a first well, a first gate coupled to the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. a charging circuit coupled to the second node and the third node, and configured to charge the third node during an ESD event at the second node.