Backside Clock Mesh Layout to Reduce Skew and Routing Contention
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Solution Overview
Problem
Conventional clock meshes in integrated circuit (IC) devices face challenges such as high power consumption, increased competition for routing resources, and potential noise interference with non-clock logic signals. Additionally, they occupy valuable space in the front side BEOL interconnect structure and can introduce delays due to skew in clock signals.
Innovation Solution
The proposed solution involves relocating the clock mesh to the backside interconnect structure, where it is formed by two sets of parallel clock lines arranged at the same level and interconnected by crossing each other. This configuration reduces competition for routing resources in the front side BEOL and minimizes noise interference. By merging the clock lines into a single common metallization layer, the need for vertical via connections is eliminated, resulting in shorter signal path lengths and reduced resistance at crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If clock mesh is implemented in front side BEOL interconnect structure, then clock distribution coverage is improved, but routing resource competition increases and power consumption increases
Solution Approach 1:
The patent moves the clock mesh from the front side BEOL interconnect structure to the backside interconnect structure, utilizing the third dimension (vertical layering) to resolve the routing resource competition. This dimensional transition allows clock signals to be distributed without competing with logic input/output signal routing resources in the front side, while still achieving comprehensive clock distribution coverage across the chip.
Solution Approach 2:
The clock distribution network is segmented into front side and backside interconnect structures. The backside interconnect structure is specifically dedicated to clock mesh implementation, while the front side focuses on logic signal routing. This segmentation separates clock distribution functions from logic signal routing functions, eliminating resource competition.
2Area of stationary object
If clock mesh is implemented in front side BEOL interconnect structure, then clock distribution coverage is improved, but power consumption increases
Solution Approach 1:
By relocating the clock mesh to the backside interconnect structure, the patent reduces the total length of clock signal paths and minimizes the number of interconnect layers required for clock distribution. This dimensional repositioning leads to lower resistance and capacitance in the clock network, thereby reducing dynamic power consumption while maintaining comprehensive clock distribution coverage.
3Area of stationary object
If clock mesh is implemented in front side BEOL interconnect structure, then clock distribution coverage is improved, but noise interference with non-clock logic signals increases
Solution Approach 1:
The patent extracts the clock mesh from the front side BEOL interconnect structure and places it in the backside interconnect structure. This extraction separates the clock signal paths from the logic signal routing paths, preventing electromagnetic noise from clock signals from interfering with sensitive logic input and output signals in the front side interconnect structure.
Solution Approach 2:
By utilizing the backside interconnect structure for clock distribution, the patent creates physical and electromagnetic isolation between clock signals and logic signals. The vertical separation in the third dimension provides natural shielding and reduces capacitive coupling, thereby minimizing noise interference while maintaining effective clock distribution coverage.
4Device complexity
If vertical via connections are used to interconnect clock lines, then three-dimensional interconnection is achieved, but signal path length increases and fabrication complexity increases
Solution Approach 1:
The patent merges all clock lines into a single common metallization layer in the backside interconnect structure. This merging eliminates the need for vertical via connections between different clock line layers, as all clock lines now exist in the same plane. The result is shorter signal path lengths and reduced fabrication complexity, while still achieving comprehensive interconnection through the crossing arrangement of clock lines.
Solution Approach 2:
Instead of using vertical vias to interconnect clock lines across multiple layers, the patent transitions to a planar configuration where all clock lines are interconnected through crossing arrangements in a single layer. This dimensional change from vertical to horizontal interconnection reduces signal path length and simplifies the fabrication process.
5Device complexity
If vertical via connections are used to interconnect clock lines, then three-dimensional interconnection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent combines all clock lines into a single metallization layer, eliminating the need for multiple via fabrication steps. This merging reduces the number of patterning, etching, and deposition cycles required, thereby simplifying the manufacturing process and reducing fabrication complexity while maintaining the necessary interconnection functionality.
Data Source
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AI summary
There is provided an integrated circuit device (10). The integrated circuit device (10) comprises a clock distribution network (30) comprising a clock mesh (32) formed by a first set of parallel clock lines (34) and a second set of parallel clock lines (36), wherein the first and second sets of clock lines (34, 36) are arranged at a same level (BSM2) in a backside interconnect structure (20) of the integrated circuit device (10) and are interconnected by crossing each other.