Backside Clock Routing in ICs for Noise-Immune Signal Isolation
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Solution Overview
Problem
Current integrated circuit designs face challenges in noise immunity due to the proximity of clock signals to data signals on the front side, leading to interference and complexity in circuit design and manufacturing.
Innovation Solution
The implementation of back side conductive lines for transmitting clock signals, interposed between power rails, enhances noise immunity by shielding clock signals from data signal interference, and optimizes circuit design and manufacturing by separating clock and supply voltage routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock signals are routed on the front side near data signals, then routing complexity is reduced, but noise immunity deteriorates due to interference
Solution Approach 1:
The patent routes clock signals on the back side of the semiconductor substrate instead of the front side, utilizing the third dimension (depth/layer) to separate clock and data signal paths. This dimensional change eliminates interference while maintaining routing efficiency, as clock signals can be distributed through dedicated back-side conductive layers without conflicting with front-side data signal routing.
2Reliability
If clock signals are separated from data signals by moving to back side, then noise immunity improves, but device complexity increases
Solution Approach 1:
The patent segments the signal routing into distinct functional zones: front side for data signals and back side for clock signals. This segmentation allows each side to be optimized independently for its specific function, reducing overall design complexity despite the multi-layer structure. The conductive layers are divided into specific regions (first conductive region for clocks, second conductive region for data) that can be designed and manufactured separately.
Solution Approach 2:
The back side conductive layers serve multiple functions: they provide clock signal distribution, act as shielding structures, and enable power/ground routing. This multi-functionality reduces the need for additional dedicated structures, thereby offsetting the increased complexity with functional consolidation.
3Reliability
If clock and supply voltage routing are separated, then noise immunity improves, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates power and ground conductive lines in the back side conductive layers during the initial substrate preparation stage, before clock signal routing is implemented. This preliminary action ensures that power/ground networks are established first, providing a stable reference framework that simplifies subsequent clock signal routing and reduces manufacturing steps.
Data Source
AI summary
An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.