Backside CMOS BioFET Fabrication via Non-Plasma Etching

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Solution Overview

Problem

The fabrication of BioFETs is challenging due to compatibility issues between semiconductor fabrication processes and biological applications, particularly due to plasma-induced damage and parasitic capacitances associated with metal interconnect layers, which limits sensitivity and integration options.

Innovation Solution

A method for fabricating BioFETs using a CMOS-compatible process that involves forming a sensing film on the backside of a semiconductor substrate, avoiding plasma etching to prevent damage, and using a non-plasma etch to expose the active region, allowing for higher sensitivity and reduced parasitic capacitances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If plasma etching is used to expose the active region, then the etching process is efficient and complete, but plasma-induced damage occurs on the semiconductor substrate

Engineering Contradiction:
Improveetching efficiencyVSAvoidplasma-induced damage
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful plasma-induced damage from the etching process by replacing plasma etching with non-plasma etching methods. This allows the useful function of exposing the active region to be maintained while removing the harmful plasma exposure that causes damage to the semiconductor substrate.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary approach by using alternative etching chemistries and processes that do not rely on plasma. This intermediary method achieves the desired etching results through non-plasma mechanisms, thereby preventing plasma-induced damage while maintaining etching effectiveness.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If metal interconnect layers are added for electrical connections, then electrical connectivity is improved, but parasitic capacitances increase and sensitivity decreases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidsensitivity
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent extracts the harmful parasitic capacitances by eliminating metal interconnect layers from the BioFET structure. By removing these layers, the unwanted capacitive effects are eliminated, allowing the device to maintain electrical connectivity through alternative means while preserving sensitivity for biomolecule detection.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of adding metal interconnect layers to achieve electrical connectivity, the patent inverts the approach by designing the device structure to inherently provide electrical connections without additional metal layers. This inversion eliminates the source of parasitic capacitances while maintaining the necessary electrical functionality.

Inventive Principle:
Principle #13The other way round (Inversion)

3Ease of manufacture

If standard CMOS fabrication processes are used, then manufacturing compatibility is maintained, but biological application requirements are not met due to plasma damage and structural limitations

Engineering Contradiction:
ImproveCMOS compatibilityVSAvoidbiological application suitability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent segments the fabrication process into distinct stages, with early stages using standard CMOS-compatible processes and later stages incorporating specialized non-plasma etching and sensing film formation. This segmentation allows the device to benefit from both standard manufacturing compatibility and specialized biological application suitability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes key process parameters by replacing plasma-based etching with non-plasma etching methods in the later fabrication stages. This parameter change maintains compatibility with CMOS manufacturing while adapting the device structure and properties to meet biological application requirements, eliminating plasma-induced damage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11099152B2Backside CMOS compatible BioFET with no plasma induced damage
Publication Date: 2021.08.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11099152B2 patent drawing
  • US11099152B2 patent drawing
  • US11099152B2 patent drawing

AI summary

The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.