Backside CMOS Trench Epi Layout for Close N2P Contact Isolation

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Solution Overview

Problem

Nanosheet technology faces interference issues when scaling down, particularly with backside source/drain contacts in microelectronic devices, as they can interfere with each other due to their proximity.

Innovation Solution

A microelectronic structure is designed with a dielectric bar between transistors, where each source/drain is flush against the dielectric bar's sidewall, and backside contacts are formed to connect the source/drain layers with varying doping concentrations, allowing for efficient contact formation without interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If nanosheet devices are scaled down and placed closer together to increase device density, then device integration is improved, but backside source/drain contacts interfere with each other

Engineering Contradiction:
Improvedevice integrationVSAvoidcontact interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

A dielectric bar is introduced as an intermediary structure between adjacent nanosheet devices. This dielectric bar physically separates the backside source/drain contacts of neighboring devices, preventing electrical interference while allowing both devices to maintain high integration density. The dielectric material acts as a mediator that isolates the contacts spatially.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The continuous substrate surface is segmented by introducing dielectric bars between adjacent nanosheet devices. This segmentation divides the device array into discrete units with clear boundaries, allowing independent formation and isolation of backside contacts for each device while maintaining overall high-density integration.

Inventive Principle:
Principle #1Segmentation

2Reliability

If backside contacts are formed to connect source/drain layers, then electrical connection is improved, but contact interference with adjacent devices occurs

Engineering Contradiction:
Improveelectrical connectionVSAvoidcontact interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The dielectric bar serves as a mediator that enables reliable electrical connection within each device while preventing interference with adjacent devices. It provides the necessary physical separation to ensure that backside contacts maintain their electrical function without cross-talk or interference from neighboring device contacts.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric bar provides localized isolation specifically at the critical interface where backside contacts are formed. This local quality enhancement ensures that electrical connections are reliable where needed (at the contact points) while preventing interference in the adjacent regions through the dielectric barrier.

Inventive Principle:
Principle #3Local quality

3Productivity

If source/drain layers are positioned close to the dielectric bar to maximize space utilization, then device density is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedevice densityVSAvoidcontact alignment
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The dielectric bar is formed in advance during the fabrication process, establishing predetermined separation regions before source/drain contact formation. This preliminary action creates well-defined boundaries and alignment references that guide subsequent contact formation steps, reducing the precision burden on later manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dielectric bar introduces a vertical dimension of separation between adjacent device planes. By utilizing the vertical stacking approach with dielectric bars positioned between devices, the design achieves high density through three-dimensional space utilization rather than relying solely on tight lateral spacing, which would demand higher lateral alignment precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12154945B2Backside CMOS trench epi with close N2P space
Publication Date: 2024.11.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12154945B2 patent drawing
  • US12154945B2 patent drawing
  • US12154945B2 patent drawing

AI summary

A microelectronic structure including a first transistor including a plurality a first channel layers. A second transistor including a plurality of second channel layers, where the first transistor is located adjacent to the second transistors. A dielectric bar located between the first transistor and the second transistor. A first source/drain of the first transistor is located on a first side of the dielectric bar and a second source/drain of the second transistor is located on a second side of the dielectric bar, where the first side is opposite the second side. A first backside contact connected to the first source/drain, where the first backside contact is in contact with first side of the dielectric bar. A second backside contact connected to the second source/drain, where the second backside contact is in contact with the second side of dielectric bar.