Backside Self-Aligned Conductive Pass-Through Contacts for Sub-10nm ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit fabrication lies in maintaining mobility and short channel control as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, where lithographic processes face constraints due to the trade-off between feature dimension and spacing, and conventional methods require complex and costly processes.
Innovation Solution
The implementation of backside self-aligned conductive pass-through contacts using a fully self-aligned mask-less process on the wafer backside, eliminating the need for immersion lithography and allowing for sub-fins with guide spacer alignment, enables cost-effective generation of backside to frontside interconnects and reduces processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lithographic processes are used to pattern features at smaller dimensions, then device density increases, but the spacing between features becomes insufficient and process complexity increases
Solution Approach 1:
The patent performs contact hole patterning from the backside of the substrate rather than the frontside, inverting the conventional approach. This allows the formation of contact holes through self-aligned etching from the opposite direction, avoiding the need for complex frontside lithographic processes at sub-10nm nodes while maintaining precise alignment through the self-aligned mechanism
Solution Approach 2:
The patent transitions the patterning operation from the frontside to the backside dimension of the substrate. By accessing the substrate from the opposite side and performing self-aligned etching, the process achieves the required feature precision without being constrained by frontside lithographic resolution limits, effectively adding a new dimensional approach to the patterning problem
2Quantity of substance
If feature dimensions are reduced to increase device density, then capacity increases, but maintaining mobility improvement and short channel control becomes challenging
Solution Approach 1:
The patent employs self-aligned etching where the contact hole positioning is automatically determined by the physical structures already present on the substrate (such as fin structures or transistor features). This self-service mechanism ensures precise alignment without requiring additional lithographic steps, thereby maintaining feature precision and short channel control even as dimensions scale to sub-10nm nodes where conventional alignment would fail
3Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then fabrication cost decreases and process complexity reduces, but maintaining performance at sub-10nm nodes becomes difficult
Solution Approach 1:
The patent inverts the conventional frontside contact formation approach by performing backside contact hole patterning. This allows multi-gate transistors to be fabricated on cost-effective bulk silicon substrates while achieving the precise contact alignment needed for sub-10nm performance through the self-aligned backside etching process, thereby maintaining both cost advantages and device performance
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Integrated circuit structures having backside self-aligned conductive pass-through contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive pass-through contacts, are described. An integrated circuit structure includes a first sub-fin structure (104) over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A dummy gate electrode (112A) is laterally between the first stack of nanowires and the second stack of nanowires. A conductive pass-through contact (130) is laterally between the first stack of nanowires and the second stack of nanowires. The conductive pass-through contact is on and in contact with the dummy gate electrode.