Backside Conductive Structures for Dense IC Routing Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit design is the difficulty in forming semiconductor devices, particularly in reducing the size of memory and logic cells, due to limited space, signal and power routing, and achieving electrical isolation to minimize parasitic effects and leakages.
Innovation Solution
The formation of integrated circuits with backside conductive structures that extend through the device layer to contact frontside contacts, using etching processes to expose and connect with frontside source or drain regions and dielectric walls, enabling efficient signal and power routing between frontside and backside contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional frontside-only contact routing is used, then device layout is simple, but signal and power routing efficiency deteriorates due to limited space and increased parasitic effects
Solution Approach 1:
The patent introduces backside contacts and through-device conductive structures that extend from the frontside through the device layer to the backside, adding a vertical dimension to the traditional planar frontside routing. This enables signals and power to be routed through the thickness of the device, effectively utilizing the third dimension to reduce routing congestion and parasitic effects while maintaining compact footprint.
Solution Approach 2:
The conductive structures are segmented into multiple regions: frontside contacts, through-device conductive structures extending through the device layer, and backside contacts. This segmentation allows independent optimization of each segment's properties and enables flexible routing paths that can be tailored to specific design requirements.
2Quantity of substance
If device size is reduced to increase density, then area utilization improves, but electrical isolation between adjacent devices deteriorates making parasitic effects and leakages more significant
Solution Approach 1:
Dielectric walls are introduced as intermediary structures that extend between adjacent through-device conductive structures and gate structures. These dielectric walls act as barriers that electrically isolate adjacent conductive paths, preventing parasitic coupling and leakage currents between neighboring devices while allowing the devices to be closely spaced for high density.
Solution Approach 2:
The dielectric walls are strategically positioned only where needed for isolation between adjacent conductive structures, rather than uniformly throughout the entire device. This localized approach provides effective parasitic reduction precisely where the through-device routing creates adjacent conductive paths that need isolation.
3Productivity
If through-device conductive structures are added to improve routing, then signal and power routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The through-device conductive structures are formed using preliminary patterning and deposition steps that define the conductive paths through the device layer before final device assembly. By establishing these conductive structures early in the fabrication sequence, subsequent processing steps can proceed without additional complexity, as the through-routes are already in place to guide subsequent isolation and connection formation.
Solution Approach 2:
The dielectric walls are formed within recesses that are themselves defined by the through-device conductive structures. The nested arrangement of conductive structures containing dielectric isolation walls within recesses allows multiple functional elements to be integrated in a hierarchical manner, reducing the number of separate fabrication cycles needed.
Data Source
AI summary
Techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. In an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. A backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.