Backside Contact Structure for Uniform 3D FET Channel Formation
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing three-dimensional designs such as multi-gate field effect transistors (FETs) like finFETs and gate-all-around FETs due to issues with channel region formation and source/drain region definition, leading to variations in device performance and reliability.
Innovation Solution
A method involving the formation of alternately stacked first and second semiconductor layers over a substrate, followed by the creation of a sacrificial gate structure, etching of source/drain regions, and epitaxial layer growth with specific deposition and etching processes to achieve uniform and precise channel and source/drain epitaxial layers, ensuring consistent device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional manufacturing methods are used for three-dimensional semiconductor designs, then device density and performance can be improved, but variations in channel region formation and source/drain region definition lead to poor manufacturing precision and device reliability
Solution Approach 1:
The channel region is formed by stacking multiple thin semiconductor layers (first and second semiconductor layers alternately stacked) rather than using a single thick layer. This segmentation into multiple thin layers enables better control over the channel region dimensions and improves manufacturing precision while maintaining the required device density.
Solution Approach 2:
A sacrificial gate structure is formed over the fin structure before etching the source/drain regions. This preliminary action defines the source/drain region boundaries with high precision before the actual etching process, ensuring consistent channel region formation across multiple devices.
2Productivity
If conventional etching methods are used for source/drain regions, then manufacturing speed can be maintained, but height and width variations in epitaxial layers result in poor device consistency
Solution Approach 1:
The epitaxial growth process uses multiple deposition and etching cycles with varying parameters. The deposition phase grows the epitaxial layer while the etching phase removes excess material. By adjusting deposition temperature, etching time, and gas flow rates between cycles, the method achieves uniform height and width of epitaxial layers across all devices while maintaining manufacturing speed.
Solution Approach 2:
The epitaxial layer formation employs periodic deposition and etching cycles rather than a single continuous process. Multiple alternating phases of deposition and etching are performed, allowing precise control over the final epitaxial layer dimensions and uniformity, thereby improving device consistency without sacrificing productivity.
3Device complexity
If single-layer semiconductor structures are used, then manufacturing process complexity can be reduced, but device performance and reliability suffer due to inability to control channel region precisely
Solution Approach 1:
The semiconductor structure uses alternating stacks of first and second semiconductor layers to form the channel region, replacing a single-layer structure. This segmentation enables precise control over channel region thickness and composition, improving device performance consistency and reliability while the process remains manageable through standardized deposition and etching cycles.
Solution Approach 2:
The channel region is formed using composite semiconductor layer structures with different materials (first semiconductor layers and second semiconductor layers with different compositions). This composite approach allows optimization of electrical properties and mechanical stability, enhancing device reliability while the manufacturing process uses conventional epitaxial growth and etching techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and precision of channel and source/drain epitaxial layers, improving the reliability and performance of FETs by reducing height and width variations, thereby improving manufacturing margins and device consistency.
Implementation Method 1
epitaxial layer growth with specific deposition and etching processes
Implementation Method 2
deposition phase
Data Source
AI summary
In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.