Self-Aligned Backside Contact Structure for 3DSFET Alignment
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Solution Overview
Problem
The formation of lower contact plugs in 3DSFETs is complicated due to overlapping source/drain regions, leading to misalignment and unwanted connections with the gate structure, especially when the lower and upper transistors have the same channel and source/drain sizes.
Innovation Solution
A self-aligned backside contact plug is formed using a contact isolation layer, which is isolated from the gate structure and extended to a region below the gate, reducing the risk of misalignment and improving contact area through the use of a shallow trench isolation region and different materials for the isolation and contact layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a backside contact plug is formed to connect to the lower source/drain region, then the connection to voltage source is achieved, but misalignment with the lower source/drain region or unwanted connection to gate structure occurs due to complicated overlay at the back side
Solution Approach 1:
A contact isolation layer is introduced as an intermediary structure between the backside contact plug and the underlying transistor components. This contact isolation layer is selectively removed to expose the lower source/drain region while providing lateral extension to define the contact opening position, thereby serving as a mediator that guides precise contact formation without direct alignment to the gate structure
Solution Approach 2:
The contact isolation layer is formed and laterally extended in advance before the backside contact plug formation. This preliminary extension creates a pre-defined template that guides the subsequent contact opening formation, ensuring the contact plug will be precisely positioned over the lower source/drain region without requiring complex overlay alignment during the contact formation process
2Ease of manufacture
If the upper channel structure and source/drain region are made smaller than the lower ones, then a non-overlapping region is created for backside contact formation, but the device density and performance are reduced
Solution Approach 1:
Instead of reducing the upper channel width in the lateral dimension to create non-overlapping regions, the invention extends the contact isolation layer laterally in the opposite lateral direction (away from the gate) to create the necessary non-overlapping region. This dimensional approach allows maintaining full upper channel width for high device density while still providing access to the lower source/drain region through the laterally extended contact isolation layer
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2~3
AI summary
A semiconductor device includes: at least one transistor comprising source/drain regions (113R, 113L) and 1st gate structure (115); a contact isolation layer (131) below the 1st gate structure; and a backside contact plug (107) connected to at least one (133R) of the 1st source/drain regions, wherein the backside contact plug is formed below the 1st source/drain region and extended to a region below the 1st gate structure (115), and isolated from the 1st gate structure by the contact isolation layer (131).