Semiconductor device with backside source/drain contact and air structure
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Solution Overview
Problem
As semiconductor devices scale down, there is a need to reduce parasitic capacitance and ensure electrical stability between contacts while maintaining device performance and reliability, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The introduction of a semiconductor device design featuring backside source/drain contacts with specific tapering and width configurations, along with air structures between source/drain patterns, to optimize electrical connections and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size of semiconductor devices is decreased to increase density, then device density is improved, but parasitic capacitance increases and electrical stability between contacts deteriorates
Solution Approach 1:
An air structure is introduced as an intermediary element between adjacent source/drain patterns. This air structure acts as a mediator that reduces parasitic capacitance between the closely spaced source/drain regions, enabling high device density while maintaining electrical stability. The air structure is positioned to overlap with the backside source/drain contact in the second direction, creating an electrical isolation effect that prevents unwanted capacitance coupling between adjacent contacts.
Solution Approach 2:
The backside source/drain contact is designed with non-uniform width characteristics - the width in the second direction decreases away from the first surface of the backside wiring line in the first portion. This local variation in geometric quality optimizes the contact's electrical performance by reducing parasitic capacitance in critical regions while maintaining adequate connection area at the source/drain interface.
2Object-generated harmful factors
If backside source/drain contact width is reduced to minimize parasitic capacitance, then parasitic capacitance is improved, but contact area and electrical connection deteriorate
Solution Approach 1:
The contact structure utilizes three-dimensional geometry with varying width in the second direction and controlled height in the third direction. By transitioning from a two-dimensional planar contact to a three-dimensional structure with tapered sides, the design reduces parasitic capacitance through reduced width while maintaining adequate electrical connection through sufficient height and optimized surface area at the interface regions.
Solution Approach 2:
The contact dimensions are optimized by changing geometric parameters - the width in the second direction varies along the height in the third direction. This parameter variation allows the contact to achieve low parasitic capacitance through reduced average width while maintaining reliable electrical connection through controlled height and interface area, balancing both requirements simultaneously.
3Object-generated harmful factors
If air structure height is increased to reduce parasitic capacitance, then parasitic capacitance is improved, but device height and manufacturing complexity increase
Solution Approach 1:
The air structure is positioned to overlap with the backside source/drain contact in the second direction, providing sufficient capacitance reduction only in the critical region where parasitic effects are most significant. This partial action approach achieves the necessary electrical isolation without requiring excessive air structure height throughout the entire device, thereby reducing manufacturing complexity while maintaining effectiveness.
Data Source
AI summary
There is provided a semiconductor device including a backside source/drain contact formed at a backside thereof to be connected to a bottom surface of a first source/drain pattern, wherein a first portion of the backside contact has a tapering shape from a backside wiring line, a second portion of the backside contact has a constant width along a vertical direction, and a sacrificial epitaxial pattern is formed in an active pattern and connected to a bottom surface of a second source/drain pattern of which a top surface is connected to a frontside source/drain contact.