Backside Contact Air Spacer for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to scale down, challenges arise in maintaining device performance and reducing fabrication costs, particularly in forming effective backside contacts for field-effect transistors, where conventional methods are not entirely satisfactory in reducing parasitic capacitance and improving device complexity.
Innovation Solution
The implementation of an air spacer, formed by depositing a sacrificial material along the sidewalls of a trench and removing it to create a gap surrounding a metal contact, which reduces capacitance and enhances device performance by using a dielectric layer and conductive material to fill the trench, thereby improving the backside contact effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside contact methods are used, then fabrication process is simpler, but parasitic capacitance is higher and device performance is reduced
Solution Approach 1:
The patent segments the backside contact structure by introducing an air spacer that divides the contact region into distinct segments: the metal contact plug, the air gap, and the underlying semiconductor region. This segmentation isolates the contact electrically from parasitic capacitance sources while maintaining the necessary electrical connection, thereby improving device performance without requiring fundamental changes to the fabrication process
Solution Approach 2:
The air spacer acts as an intermediary element between the metal contact plug and the underlying semiconductor structures. This intermediary air gap provides electrical isolation that reduces parasitic capacitance while still allowing the contact to function properly. The air spacer mediates between the conflicting requirements of maintaining low parasitic capacitance and preserving simple fabrication processes
2Productivity
If device geometry is scaled down, then production efficiency increases and costs decrease, but device performance degradation and fabrication complexity increase
Solution Approach 1:
The patent applies parameter changes by modifying the physical dimensions and electrical properties of the backside contact structure. Specifically, the air spacer introduces a controlled change in the electrical parameters (reducing parasitic capacitance) while maintaining geometric scaling. This allows continued scaling for improved productivity while preserving device performance through the modified contact structure parameters
3Area of stationary object
If device geometry is scaled down, then chip area decreases and production efficiency increases, but fabrication complexity and device performance challenges increase
Solution Approach 1:
The air spacer structure is formed as a preliminary feature during the backside contact fabrication process. By pre-establishing the air gap structure before final contact formation, the patent simplifies subsequent processing steps while ensuring the contact structure is optimized for reduced parasitic capacitance from the outset, thereby managing fabrication complexity during scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, improving the performance of field-effect transistors by creating an air gap that enhances the effectiveness of the backside contact, allowing for better gate control and reduced short-channel effects, while maintaining aggressive scaling and compatibility with CMOS processes.
Implementation Method 1
depositing a sacrificial material along the sidewalls of a trench and removing it to create a gap surrounding a metal contact
Data Source
AI summary
A semiconductor structure includes an active region including a source/drain feature, a contact protruding from a bottom surface of the source/drain feature, a first dielectric layer disposed directly below the active region and surrounding the contact, an air gap disposed between the contact and the first dielectric layer, and a seal disposed between the contact and the first dielectric layer, such that the air gap is disposed between the seal and the source/drain feature.