Backside Contact Structure for Void-Free BSPDN Power Rails
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Solution Overview
Problem
Conventional methods for forming direct backside contacts (DBC) in semiconductor devices face challenges such as patterning issues and high aspect ratio etch processes, leading to void formation and alignment difficulties, especially as contacted poly pitch becomes narrower.
Innovation Solution
A semiconductor device structure is developed with a backside power delivery network (BSPDN) that omits a bottom dielectric isolation layer, featuring a direct backside contact (DBC) with a positive etch slope and dielectric material barrier, ensuring alignment and void-free conductive material fill, and includes a semiconductor buffer layer between the DBC and the source/drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If direct backside contact (DBC) is formed using conventional methods, then power delivery is achieved, but patterning issues and alignment difficulties occur especially in narrow contacted poly pitch environments
Solution Approach 1:
The patent introduces a dielectric material barrier as an intermediary layer between the backside contact and the source/drain region. This barrier layer acts as a mediator that facilitates precise alignment and prevents direct contact where shorts could occur, thereby solving the alignment precision issue in narrow pitched structures
Solution Approach 2:
The patent forms the dielectric material barrier and isolation regions before completing the backside contact formation. This preliminary action establishes precise geometric boundaries and alignment references that guide subsequent contact formation, preventing alignment issues before they occur
2Length of stationary object
If high aspect ratio etch process is used for DBC formation, then deep contact holes are created, but void formation occurs
Solution Approach 1:
The patent creates a positive etch slope in the contact hole by using selective etching processes that modify the local geometry. The contact hole transitions from a uniform cylinder to a tapered shape with wider opening, which improves material fill reliability and prevents void formation while maintaining the required depth
Solution Approach 2:
The patent changes the geometric parameters of the contact hole during the etching process, specifically creating a positive etch slope that widens the opening relative to the bottom. This parameter change from a vertical-walled hole to a tapered hole improves subsequent material deposition and eliminates voids
3Reliability
If bottom dielectric isolation layer is included in DBC structure, then isolation is provided, but alignment difficulties and process complexity increase
Solution Approach 1:
The patent merges the isolation function with the contact structure by forming isolation regions that are integrated into the contact formation process. The isolation regions are created alongside the contact holes in a unified process sequence, eliminating the need for a separate bottom dielectric isolation layer and reducing overall structure complexity
Solution Approach 2:
The dielectric material barrier serves multiple functions simultaneously: it provides electrical isolation, establishes alignment references, and prevents shorts. This multi-functionality replaces what would otherwise require separate dedicated structures, simplifying the overall device architecture
Data Source
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AI summary
Semiconductor devices are provided. A semiconductor device (110) includes a source/drain, S/D, region (140). The semiconductor device (110) includes a backside, BS, contact (150, 150a, 150b) that includes an upper surface that is on a lower surface of the S/D region (140). Moreover, the semiconductor device includes a BS power rail (160) that is on a lower surface of the BS contact and is electrically connected to the S/D region (140) by the BS contact (150, 150a, 150b). The lower surface of the BS contact (150, 150a, 150b) is wider than the upper surface of the BS contact (150, 150a, 150b). Related methods of forming semiconductor devices are also provided.