Backside Source-Drain Contact Layout With Buffer Layer Alignment
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques face challenges in accurately forming backside contacts, leading to overlay misalignment issues and potential damage to the bottom dielectric isolation layer and gate material during the formation process.
Innovation Solution
The implementation of controllable buffer layers adjacent to the bottom dielectric isolation layer allows for controlled access to the source and drain regions, protecting the layer from etching processes and eliminating the need for self-alignment techniques, thereby improving overlay margin control and preventing damage to the gate and bottom dielectric isolation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional frontside contact schemes are used, then overlay alignment is accurate and easy to control, but backside contact formation cannot be achieved
Solution Approach 1:
The patent implements backside contact formation by inverting the conventional approach: instead of forming contacts from the frontside, the method forms contacts from the backside of the wafer. This is achieved by removing the substrate from the backside to expose the bottom dielectric isolation layer, then forming contacts through this layer to reach the source and drain regions. This inversion enables backside contact capability while maintaining alignment accuracy through the buffer layer mechanism.
Solution Approach 2:
The patent introduces a buffer layer as an intermediary element between the bottom dielectric isolation layer and the source/drain regions. This buffer layer serves as a mediator that facilitates precise overlay alignment during backside contact formation. The buffer layer provides a reference plane that is easier to align with frontside features than directly aligning with the source and drain regions, thus enabling accurate backside contact formation.
2Ease of manufacture
If backside contact formation is attempted without buffer layers, then direct access to source and drain regions is achieved, but damage to bottom dielectric isolation layer and gate material occurs
Solution Approach 1:
The patent applies beforehand cushioning by depositing a buffer layer on the bottom dielectric isolation layer prior to forming the backside contact. This buffer layer acts as a protective cushion during the contact formation process, preventing direct exposure and potential damage to the bottom dielectric isolation layer and gate material. The buffer layer absorbs the mechanical and chemical stresses of the fabrication process, ensuring the integrity of underlying sensitive structures.
Solution Approach 2:
The buffer layer serves as an intermediary protective layer between the etching processes used to form backside contacts and the sensitive bottom dielectric isolation layer and gate material. This intermediary layer allows the etching to proceed safely without directly exposing or damaging the underlying structures, thus preventing harmful effects while enabling direct access to source and drain regions.
3Manufacturing precision
If self-aligned techniques are used for backside contact, then alignment precision is improved, but process complexity increases
Solution Approach 1:
The buffer layer acts as an intermediary reference structure that simplifies the alignment process. Instead of requiring complex self-aligned techniques to directly align backside contacts with source and drain regions, the buffer layer provides a stable, easily alignable reference plane. Frontside features can be aligned with the buffer layer using standard photolithographic techniques, and the buffer layer's position relative to the source and drain regions is predetermined by the fabrication process, thus reducing overall process complexity while maintaining precision.
Solution Approach 2:
The buffer layer is deposited in advance during the frontside fabrication process, before backside contact formation is attempted. This preliminary action establishes a reference structure that will be used for alignment during subsequent backside processing. By performing this alignment reference creation early in the process, the patent eliminates the need for complex real-time self-alignment techniques during backside contact formation, thus reducing process complexity while maintaining manufacturing precision.
Data Source
AI summary
A semiconductor device includes a transistor device, including a source and drain region, and a gate region. A bottom dielectric isolation layer is on a backside of the transistor device. A buffer layer is on a backside of the bottom dielectric isolation layer. A first conductive contact is positioned on a backside of the transistor device in contact with a backside of the source and drain region, through the bottom dielectric isolation layer and through the buffer layer. A second conductive contact is in contact with the gate region from a frontside of the gate region.