Backside Contact Cavity Etching to Prevent Voids and Seams
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Solution Overview
Problem
The formation of backside contacts in transistors often results in voids and seams due to the increasing width of trenches from the backside of the transistor towards the frontside, which affects the reliability and density of the device.
Innovation Solution
A two-step etching process is employed, where a first removal process forms a trench and a subsequent wet etch forms a cavity below the channel structures, ensuring the backside contact width decreases from the backside to the source/drain region, mitigating voids and seams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to form the trench for backside contact, then the manufacturing process is simple, but voids and seams form due to increasing trench width from backside to frontside
Solution Approach 1:
The etching process is divided into two distinct steps: a first etching process that forms the initial trench, and a second etching process that forms the cavity below the channel structures. This segmentation allows each etching step to be optimized independently, preventing void and seam formation while maintaining manufacturing feasibility.
Solution Approach 2:
The first etching process creates a preliminary trench structure that defines the backside contact region. This preliminary action establishes the foundation for the subsequent cavity formation, ensuring proper geometry is achieved before final cavity etching occurs.
2Productivity
If trench width increases from backside to frontside to accommodate device structure, then device density is improved, but voids and seams are generated in the backside contact
Solution Approach 1:
The solution addresses the width variation problem by extending the trench vertically into a cavity below the channel structures. This dimensional change allows the backside contact to maintain consistent width through the cavity region, preventing voids and seams while still accommodating the required device density through proper spatial arrangement.
Solution Approach 2:
The cavity formation creates a localized region with uniform width characteristics specifically where the backside contact is formed. This local quality control ensures consistent contact geometry in the critical backside region without compromising the overall device structure and density requirements.
3Reliability
If backside contact width is reduced to eliminate voids, then contact reliability improves, but device density and packaging efficiency decrease
Solution Approach 1:
By forming the backside contact within a vertically extended cavity rather than constraining it to a narrow horizontal width, the invention maintains contact integrity through proper cavity geometry while preserving packaging efficiency through optimized spatial utilization of the three-dimensional contact structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and density of transistors by reducing defects in the backside contact, allowing for more efficient use of both frontside and backside packaging.
Implementation Method 1
a subsequent wet etch forms a cavity below the channel structures
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.