Backside Contact Layout for Semiconductor Cell Height Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving miniaturization and complex chip layouts due to increased demands for higher integration density, lower power consumption, and faster speeds, which complicates the production of semiconductor dies with effective backside contacts.
Innovation Solution
The implementation of dielectric isolation pillars between FETs, with source/drain epi regions connected to both backside power delivery networks and back-end-of-line components, allows for gate extensions that are less than the suspension thickness between horizontal channels, enabling cell height scaling and improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional frontside contact structures are used, then manufacturing process is simpler, but integration density and miniaturization are limited
Solution Approach 1:
The patent transitions from conventional frontside contacts to backside contacts, utilizing the vertical dimension (substrate backside) to establish electrical connections. This dimensional shift allows power and signal delivery networks to be routed from the opposite side of the substrate, enabling more flexible chip layout designs and higher integration density without increasing lateral footprint.
Solution Approach 2:
The invention segments the contact structure into multiple components: backside contact openings, conductive plugs, interlayer dielectric layers, and frontside contact pads. This segmentation allows independent optimization of each layer and enables complex routing paths that improve integration density while managing manufacturing complexity through standardized process modules.
2Reliability
If backside contacts are implemented with complex routing, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps where backside contact openings are defined and formed before subsequent deposition and planarization steps. This preliminary action establishes precise alignment references that guide subsequent manufacturing steps, ensuring accurate electrical connectivity while managing precision requirements through a staged fabrication process.
Solution Approach 2:
The invention introduces interlayer dielectric layers and conductive plugs as intermediary structures between the backside contact openings and the frontside active regions. These intermediaries provide mechanical support, electrical connection, and alignment tolerance, thereby improving reliability while reducing the direct precision requirements between backside openings and frontside contacts.
3Quantity of substance
If cell height is reduced for miniaturization, then integration density increases, but structural stability and electrical performance deteriorate
Solution Approach 1:
By moving contacts to the backside of the substrate, the invention creates additional vertical space and structural support pathways. The backside contact structure extends through the substrate thickness, providing mechanical reinforcement that maintains structural stability even when cell heights are reduced for higher integration density.
Solution Approach 2:
The patent utilizes composite structures combining different materials with complementary properties: conductive materials for electrical connection, dielectric materials for insulation and mechanical support, and potentially reinforced substrate materials. This composite approach maintains structural integrity while enabling miniaturization and higher integration density.
Data Source
AI summary
A semiconductor structure is presented including a first dielectric isolation pillar disposed between a pair of p-type field effect transistors (pFETs), a second dielectric isolation pillar disposed between a pair of n-type FETs (nFETs), a first source/drain (S/D) epi region having a first contact electrically connected to a backside power delivery network (BSPDN), the first contact being disposed on one side of the first dielectric isolation pillar, and a second S/D epi region having a second contact electrically connected to back-end-of-line (BEOL) components, the second contact being disposed on the other side of the first dielectric isolation pillar.