Self-Aligned Backside Contact for Deep Trench Power Routing
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Solution Overview
Problem
As semiconductor devices become more dense, there is a need to separate power lines from data lines by placing them on different sides of the device, and existing technologies face challenges in forming efficient backside contacts and connections.
Innovation Solution
A method is developed to form a semiconductor device with a first source/drain epitaxy and a gate contact on the top side, and a backside trench epitaxy connected to a backside power distribution network, involving steps like forming a backside contact trench, filling it with sacrificial material, removing the substrate, and growing backside trench epitaxy to create a self-aligned backside contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If power lines and data lines are placed on the same side of the device, then routing is simpler, but signal/power interference increases
Solution Approach 1:
The patent implements backside contact architecture where power lines are routed through the substrate from the backside to the frontside, utilizing the third dimension (vertical depth) to separate power and data lines spatially. This dimensional transition allows power distribution networks to be formed on the backside while data lines remain on the frontside, eliminating interference while maintaining routing efficiency
2Object-affected harmful factors
If backside contact architecture is implemented, then power line separation is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial material in the backside contact trenches before substrate removal, and by pre-forming the power distribution network layers on the backside before final device assembly. These preliminary steps simplify the overall manufacturing process by establishing the backside contact structure early in the fabrication sequence
Solution Approach 2:
The patent uses sacrificial material as an intermediary substance that is temporarily placed in backside contact trenches, then removed after serving its purpose of defining the contact region. This intermediary approach enables precise backside contact formation without requiring complex direct etching or patterning of the substrate
3Area of stationary object
If device density is increased, then area utilization improves, but space constraints in BEOL layer increase
Solution Approach 1:
The patent relocates power distribution networks from the traditional frontside BEOL layer to the backside of the substrate, utilizing the vertical dimension to create additional routing space. This allows the frontside BEOL layer to be used exclusively for data lines and signaling, while power lines are distributed through backside contacts and substrate routing, effectively doubling the available routing area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for efficient electrical connections on both the top and backside of semiconductor devices, reducing signal/power interference and minimizing space constraints in the back end of the line layer.
Implementation Method 1
removing the sacrificial material to form a cavity
Implementation Method 2
growing backside trench epitaxy in the cavity
Data Source
AI summary
A semiconductor device includes first source/drain (S/D) epitaxy and a second S/D epitaxy and a gate contact. The device also includes a back end of the line (BEOL) layer electrically connected to the first S/D epitaxy and the gate contact on a top side of the device and a wafer that carries the BEOL layer and is on the top side of the device. The device also includes a backside trench epitaxy formed through and contacting portions of the second S/D epitaxy and a backside power distribution network electrically coupled to the backside trench epitaxy and disposed on the bottom of the device.