Backside Contact Layout for Dense-Pitch CMOS Source/Drain Regions
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Solution Overview
Problem
Existing semiconductor device structures with a dense gate pitch of 48-54 nm face challenges in forming reliable backside contacts to neighboring source/drain epitaxial regions, often resulting in single contacts or placeholder elements that do not connect to backside power rails.
Innovation Solution
The semiconductor device incorporates first and second backside contacts to connect neighboring source/drain epitaxial regions to a backside power rail or different power rails, with backside insulation isolating these contacts, and includes a method to form these contacts through precise alignment and insulation filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dense gate pitch of 48-54 nm is used, then device integration density is improved, but reliable backside contact formation becomes difficult
Solution Approach 1:
The patent divides a single backside contact structure into multiple separate backside contacts (first backside contact and second backside contact), each connecting to different source/drain epitaxial regions. This segmentation allows each contact to be independently formed and optimized, improving reliability while maintaining dense gate pitch configurations
Solution Approach 2:
The patent transitions from planar contact formation to three-dimensional contact formation by creating contacts through the thickness of the substrate. The backside contacts extend from the rear surface through the substrate to connect with source/drain regions, adding a vertical dimension to contact formation that enables reliable connections in dense gate pitch structures
2Reliability
If separate backside contacts are formed for neighboring source/drain epitaxial regions, then connection reliability is improved, but device complexity increases
Solution Approach 1:
The backside contacts serve multiple functions: they provide electrical connection to source/drain regions, act as alignment references for subsequent processing steps, and enable independent biasing of adjacent transistor regions. This multi-functionality justifies the additional structural elements while providing tangible benefits beyond simple connectivity
Solution Approach 2:
The first and second backside contacts are formed early in the fabrication process, before many subsequent processing steps. These preliminary contacts serve as alignment references and structural guides for later steps, simplifying subsequent processing despite the initial added complexity
Data Source
AI summary
A semiconductor device is provided and includes an active region, first, second and third gate regions disposed across the active region, a first source/drain (S/D) epitaxial region interposed between the first and second gate regions, a second S/D epitaxial region interposed between the second and third gate regions, backside metallization, a first backside contact to connect the first S/D epitaxial region to the backside metallization, a second backside contact to connect the second S/D epitaxial region to the backside metallization and backside insulation disposed to isolate the first and second backside contacts from one another.