Vertical Backside-Contact Diodes for Low-Capacitance ESD Protection

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Solution Overview

Problem

Designing diodes for ESD protection applications poses challenges, particularly in configurations where the bulk substrate is removed, as they cannot rely on the bulk substrate for current conduction, leading to issues with current carrying capability and parasitic capacitance.

Innovation Solution

A vertical diode structure is developed with a sub-fin comprising differently doped portions, allowing current to flow vertically through the sub-fin and reducing parasitic capacitance between anode and cathode contacts, suitable for high-frequency applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the bulk substrate is removed from the diode structure, then parasitic capacitance between anode and cathode contacts is reduced, but current carrying capability deteriorates

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidcurrent carrying capability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The bulk substrate is segmented into multiple thin fin structures that extend from the first contact to the second contact. This segmentation maintains current conduction paths while reducing the lateral area available for parasitic capacitance formation between anode and cathode contacts.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The current conduction path is transitioned from a lateral path through the bulk substrate to a vertical path through the fin structures. This dimensional change allows the substrate to be removed laterally while maintaining current conduction through the vertically extending fins, thereby reducing parasitic capacitance without sacrificing current carrying capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a vertical diode structure with sub-fin is used, then current carrying capability is enhanced, but device complexity increases

Engineering Contradiction:
Improvecurrent carrying capabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple fin structures are merged into a single integrated vertical diode device that shares common contacts and substrate interaction. This merging approach enhances current carrying capability through combined fin conduction paths while avoiding the complexity of multiple separate devices requiring individual contacts and interconnections.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The vertical diode structure enhances current carrying capability and reduces parasitic capacitance, making it suitable for high-frequency applications and ESD protection in integrated circuits.

Implementation Method 1

one or more diffusion regions doped with a second type of dopant, the diffusion regions in contact with the sub-fin

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

a sub-fin having at least a portion that is doped with a first type of dopant, one or more diffusion regions doped with a second type of dopant

Methodology Applied
Scientific Effectpn junction:

Data Source

PatentUS20240088131A1Diodes with backside contact
Publication Date: 2024.03.14 INTEL CORP
  • US20240088131A1 patent drawing
  • US20240088131A1 patent drawing
  • US20240088131A1 patent drawing

AI summary

An integrated circuit structure includes a sub-fin having at least a portion that is doped with a first type of dopant, and a diffusion region doped with a second type of dopant. The diffusion region is in contact with the sub-fin and extends upward from the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. In an example, a first conductive contact is above and on the diffusion region, and a second conductive contact is in contact with the portion of the sub-fin. In an example, the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode.