Backside Contact Trenches With Epitaxial Doping for Low Resistance
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Solution Overview
Problem
In integrated circuit fabrication, the metallization on both sides (MOBS) scheme faces challenges with poor ohmic contact resistance at the backside of semiconductor devices, leading to degraded transistor performance and increased parasitic capacitance, which affects cost and reliability.
Innovation Solution
The implementation of epitaxial deposition of highly doped crystalline semiconductor material in backside contact trenches, combined with a backside source/drain etch-stop layer, reduces contact resistance and eliminates parasitic external resistance, allowing for reduced metallization layers and improved die-yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallization on both sides (MOBS) scheme is implemented, then transistor performance is improved and parasitic capacitance is reduced, but backside contact resistance increases leading to poor ohmic contact
Solution Approach 1:
The patent applies parameter changes by heavily doping the semiconductor material in the backside contact region (e.g., phosphorus doping at concentrations of 1E19 to 1E21 atoms/cm³) to alter the electrical properties and reduce contact resistance. This changes the resistivity parameter of the contact region to achieve better ohmic contact while maintaining the MOBS architecture benefits
Solution Approach 2:
The patent introduces an intermediary heavily doped semiconductor layer between the backside metal contact and the lightly doped source/drain region. This intermediate layer acts as a mediator that facilitates charge carrier transport and reduces the contact resistance interface, enabling effective ohmic contact without compromising transistor performance
2Device complexity
If backside contacts are formed without additional doping, then process complexity is reduced, but contact resistance increases degrading device performance
Solution Approach 1:
The patent applies preliminary action by forming the heavily doped semiconductor layer during the front-end-of-line (FEOL) processing stage, before backside contact formation. This preliminary doping action prepares the contact region in advance, enabling low-resistance contacts without adding complex post-processing steps for contact formation
3Ease of manufacture
If standard doping concentrations are used in backside contacts, then manufacturing simplicity is maintained, but ohmic contact properties are insufficient leading to high contact resistance
Solution Approach 1:
The patent changes the doping concentration parameter from standard levels (1E18 atoms/cm³) to heavily doped levels (1E19 to 1E21 atoms/cm³) in the backside contact region. This parameter change achieves superior ohmic contact properties while using conventional semiconductor fabrication techniques, maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances ohmic contact properties, reduces parasitic capacitance, and decreases the number of metallization layers needed, resulting in cost savings and improved transistor performance.
Implementation Method 1
epitaxial deposition of highly doped crystalline semiconductor material in backside contact trenches
Data Source
Figure 1
Figure 2A~2A'
Figure 2B~2C
AI summary
Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material. Other embodiments may be described and/or disclosed.