Backside Contact Filler Structure for Dense Nanosheet MOSFET Isolation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical and reliability characteristics.

Innovation Solution

A semiconductor device design featuring a substrate with active patterns, channel patterns, gate electrodes, source/drain patterns, backside contacts, and a filler structure with a filling pattern and liner, which includes a filler portion and contact portion, addresses the issue by enhancing electrical and reliability characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If MOS-FETs are scaled down to meet increasing demand for smaller pattern size, then device size is reduced, but operational properties deteriorate

Engineering Contradiction:
Improvedevice sizeVSAvoidoperational properties
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent transitions from planar 2D MOS-FET structures to three-dimensional vertically stacked channel patterns (nanosheets or nanowires), enabling continued scaling of device footprint while maintaining operational performance through increased vertical channel area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple channel patterns are stacked vertically within a single device footprint, with gate electrodes wrapping around or positioned between stacked semiconductor layers, creating a nested configuration that multiplies effective channel area without increasing lateral dimensions

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If backside contacts are placed close together to increase density, then device integration is improved, but electrical isolation between contacts becomes difficult

Engineering Contradiction:
Improvedevice integrationVSAvoidelectrical isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A filler structure comprising an insulating filling pattern and a liner is introduced between adjacent backside contacts, serving as an intermediary element that provides electrical isolation while allowing the contacts to remain in close proximity for high integration density

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The region between backside contacts is segmented into distinct functional zones: the filler structure for isolation, the liner for protection and interface management, and the contacts themselves, enabling independent optimization of each element

Inventive Principle:
Principle #1Segmentation

3Reliability

If filler structure is added between backside contacts for isolation, then electrical isolation is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation function is extracted from the substrate material itself and implemented as a separate, dedicated filler structure between contacts, allowing the substrate to maintain its primary semiconductor function while isolation is handled by specialized insulating materials

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250351415A1Semiconductor device
Publication Date: 2025.11.13 SAMSUNG ELECTRONICS CO LTD
  • US20250351415A1 patent drawing
  • US20250351415A1 patent drawing
  • US20250351415A1 patent drawing

AI summary

A semiconductor device may include a substrate including an active pattern, a lower power line in a lower portion of the substrate, a channel pattern on the active pattern and including a plurality of semiconductor patterns, which are stacked and include a first semiconductor pattern at the lowermost level, a gate electrode crossing the active pattern and including a first inner gate electrode between the active pattern and the first semiconductor pattern, source/drain patterns on the substrate, backside contacts connecting the lower power line to the source/drain patterns, and a filler structure between adjacent backside contacts among the backside contacts. The filler structure may include a filling pattern and a liner. The filling pattern may include a contact portion on a filler portion, and the liner may cover opposite side surfaces of the filler portion. The contact portion may be in direct contact with the substrate.