Backside Source/Drain Contact Layout for Low-Parasitic Fin ICs
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Solution Overview
Problem
As integrated circuit (IC) devices downscale, they require high operating speed and accuracy, necessitating stable and optimized wiring structures within a small area while minimizing parasitic capacitance and resistance.
Innovation Solution
The IC device incorporates a fin-type active region with a back side source/drain contact and an etch stop layer, along with a device isolation film, to ensure sufficient insulation and reduce resistance, and features a self-aligned etching process for forming contact spaces, allowing for efficient alignment of source/drain contacts without strict design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the area of IC device is reduced to accommodate downscaling, then integration density is improved, but parasitic capacitance between wiring structures increases
Solution Approach 1:
The patent introduces a back side contact structure that extends contacts to the rear surface of the substrate, utilizing the third dimension (vertical depth) to separate signal paths. This dimensional transition allows wiring structures to be routed through different layers and depths, increasing the effective insulation distance between conductive elements even when planar area is constrained, thereby reducing parasitic capacitance while maintaining high integration density.
2Area of moving object
If wiring structures are arranged in a small area, then integration density is improved, but resistance of power and signal wirings increases
Solution Approach 1:
The back side contact structure enables power and signal wirings to traverse through the substrate depth, creating three-dimensional conduction paths. This allows for longer, more optimized wiring routes that can maintain lower resistance by utilizing vertical stacking and multi-layer routing, rather than being constrained to short planar paths on the surface.
Solution Approach 2:
The patent implements a multi-layer nested wiring architecture where conductive structures are arranged in stacked layers at different depths within the substrate. This nesting approach allows multiple wiring paths to coexist in a compact volume, providing both low-resistance connections and sufficient separation to minimize parasitic effects.
3Manufacturing precision
If strict design rules are applied for contact alignment, then manufacturing precision is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent employs self-aligned fabrication processes where the back side contact structures are automatically positioned relative to front side features through sequential processing steps. The etch stop layers and sacrificial structures serve as self-aligning references, eliminating the need for complex external alignment procedures and reducing fabrication complexity while maintaining high precision.
Data Source
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AI summary
An integrated circuit device includes a fin-type active region including a first fin portion and a second fin portion apart from each other in a first lateral direction with a contact space therebetween, a first source/drain region on the fin-type active region at a position overlapping the contact space in a vertical direction, a gate line on the first fin portion, a device isolation film covering both sidewalls of each of the first and second fin portions and defining a width of the contact space, a back side source/drain contact electrically connected to the first source/drain region, filling the contact space, and having a sidewall facing each of the first and second fin portions and the device isolation film, and an etch stop layer contacting a top surface of each of the first and second fin portions between the first fin portion and the gate line.