Backside Contact Layout for Gate-All-Around Nanowire Transistors
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to reduce contact resistance while maintaining mobility and short channel control, particularly in multi-gate transistors, where the constraints on lithographic processes become overwhelming as feature dimensions shrink below the 10 nanometer node, leading to a trade-off between critical dimension and spacing.
Innovation Solution
The implementation of a self-aligned backside contact process with enhanced area relative to the epitaxial source or drain region, utilizing anisotropic and isotropic etches to create a reentrant profile, and a protective helmet layer to form a conductive contact structure without voids, enabling self-aligned placement of an etch stop and reducing capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional front-side contact processes are used, then alignment is straightforward, but contact area is limited and contact resistance is high
Solution Approach 1:
The patent inverts the conventional contact formation approach by forming contacts from the backside of the substrate rather than the front side. This allows the contact opening to be formed after the transistor structures are already in place, enabling the contact area to be enlarged without compromising the critical dimensions of the transistor features. The backside contact approach achieves both good alignment (through self-alignment to the epitaxial region) and low contact resistance (through increased contact area).
Solution Approach 2:
The patent transitions from two-dimensional front-side contact formation to three-dimensional backside contact formation. By accessing the substrate from the backside and creating a reentrant profile contact opening that extends laterally beneath the epitaxial source/drain region, the contact area is significantly increased without occupying additional planar space on the front side. This dimensional change resolves the contradiction between limited contact area and high contact resistance.
2Productivity
If feature dimensions are reduced below 10 nanometer node, then device density increases, but lithographic constraints become overwhelming with trade-off between critical dimension and spacing
Solution Approach 1:
The patent inverts the sequence of contact formation relative to transistor fabrication. Instead of forming contacts before transistor structures (conventional approach), contacts are formed after transistors are complete. This self-aligned backside contact approach eliminates the need for additional lithographic spacing between contact openings and transistor features, as the contact opening is defined by the epitaxial region itself rather than by a separate lithographic pattern. This resolves the lithographic spacing constraint while maintaining high device density.
3Reliability
If contact area is increased to reduce contact resistance, then contact resistance decreases, but capacitive coupling increases
Solution Approach 1:
The patent segments the contact formation process into distinct stages: first forming the contact opening through the substrate to the epitaxial region, then filling with conductive material. The reentrant profile design segments the contact area into a large bottom area (for low resistance) and a narrow opening area (for minimal capacitive coupling). This segmentation allows the contact area to be enlarged without proportionally increasing the capacitive coupling, as the capacitive coupling is primarily determined by the opening area rather than the total contact area.
Solution Approach 2:
The patent applies different geometric characteristics to different parts of the contact structure. The bottom of the contact opening has a large area to minimize contact resistance, while the opening itself has a narrow profile to minimize capacitive coupling. This local quality variation within the contact structure resolves the contradiction between low contact resistance and minimal capacitive coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves reduced contact resistance without increasing capacitive coupling, providing a more robust process flow with improved yield and relaxed lithography specifications, allowing for tighter spacing and increased area efficiency.
Implementation Method 1
utilizing anisotropic and isotropic etches to create a reentrant profile
Implementation Method 2
utilizing anisotropic and isotropic etches to create a reentrant profile
Implementation Method 3
a protective helmet layer to form a conductive contact structure without voids
Data Source
AI summary
Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.