Backside Source/Drain Contact Gap With Low-k Spacer Isolation
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Solution Overview
Problem
As semiconductor devices shrink, the close proximity of source/drain contacts and gate contacts increases parasitic capacitance, reducing switching speed and process windows, which existing backside power rail formation processes do not adequately address.
Innovation Solution
A method is developed to form a backside source/drain contact spaced apart from adjacent structures by a gap, involving a sacrificial plug, hard mask formation, and selective etching to create a gap between the backside source contact and dielectric layer, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain contacts and gate contacts are placed in close proximity to increase packing density, then functional density is improved, but parasitic capacitance increases reducing switching speed
Solution Approach 1:
The patent moves power rail routing from the front side to the back side of the substrate, utilizing the third dimension (depth/thickness) to resolve the spatial conflict. By forming backside power rails that extend through openings in the substrate, the design achieves high packing density on the front side while maintaining electrical isolation from gate structures, thus reducing parasitic capacitance without sacrificing switching speed.
2Area of stationary object
If backside power rails are formed close to gate structures to reduce routing length, then device area is reduced, but parasitic capacitance between backside contacts and gate structures increases
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the backside power rail and the gate structure. This dielectric layer acts as an electrical insulator that allows the power rail to be positioned close to the gate structure for compact area, while simultaneously preventing direct electrical interaction that would create parasitic capacitance. The dielectric material fills the space between these components, mediating their spatial proximity without electrical coupling.
3Ease of manufacture
If existing backside power rail formation processes are used, then manufacturing simplicity is maintained, but parasitic capacitance reduction is insufficient
Solution Approach 1:
The patent performs preliminary actions by forming the dielectric layer and creating isolated openings in the substrate before finalizing the backside power rail structure. The substrate is prepared with pre-defined isolation regions and dielectric filling, which establishes the capacitance-reducing architecture in advance. This preliminary structuring allows subsequent power rail formation to automatically achieve low parasitic capacitance without requiring complex additional process steps.
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.