Backside Source/Drain Contact Layout for Gate-Safe Alignment

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Solution Overview

Problem

Existing semiconductor devices face challenges in forming backside source/drain contacts without damaging gate electrodes due to overlay shifts during photolithographic processes, leading to potential damage to underlying structures.

Innovation Solution

Incorporation of sacrificial dielectric structures on gate regions or metal gate electrodes that protect the gate regions during the formation of backside source/drain contacts, allowing for self-aligned contact formation even with patterning window shifts, and enabling the contacts to fully land on epitaxial source/drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If backside source/drain contacts are formed without sacrificial dielectric structures, then the manufacturing process is simpler, but gate electrodes may be damaged due to overlay shifts during photolithographic processes

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidgate electrode integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A sacrificial dielectric structure is introduced as an intermediary element between the gate electrode and the etching process. This mediator absorbs the impact of overlay shifts by providing a buffer layer that prevents direct contact between the etchant and the gate electrode, thus protecting the gate while enabling contact formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial dielectric structure is formed in advance before the backside source/drain contact formation process. This preliminary action prepares the structure to accommodate potential overlay shifts during subsequent photolithographic steps, ensuring gate electrode protection is already in place before damage can occur.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If sacrificial dielectric structures are used to protect gate regions, then gate electrode damage is prevented, but the device structure becomes more complex

Engineering Contradiction:
Improvegate electrode protectionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial dielectric structure serves as a temporary element that is discarded after fulfilling its protective function. It is removed after the backside source/drain contacts are successfully formed, leaving no permanent trace in the final device. This approach adds complexity only during the manufacturing process, not in the final product.

Inventive Principle:
Principle #34Discarding and recovering

Solution Approach 2:

The sacrificial dielectric structure is designed as a disposable, low-cost component that exists only temporarily during fabrication. Its temporary presence enables complex protective functionality during manufacturing, but it is completely removed before the device is finalized, so the complexity does not persist in the end product.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Manufacturing precision

If patterning windows are enlarged to tolerate overlay shifts, then manufacturing precision is improved, but the risk of damaging underlying structures increases

Engineering Contradiction:
Improveoverlay shift toleranceVSAvoiddamage risk to underlying structures
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The sacrificial dielectric structure acts as a pre-positioned cushioning layer that absorbs the harmful effects of overlay shifts. By placing this protective buffer beforehand, the structure can tolerate larger patterning window variations without transmitting damage to the gate electrode or other underlying sensitive structures.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20250366036A1Semiconductor device having front side and back side source/drain contacts
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250366036A1 patent drawing
  • US20250366036A1 patent drawing
  • US20250366036A1 patent drawing

AI summary

A device includes semiconductor device structure includes a first dielectric layer. A first plurality of nanostructures are disposed on the first dielectric layer, with the first plurality of nanostructures overlying one another. A first source/drain region is disposed laterally adjacent to a first side of the first plurality of nanostructures. A second dielectric layer is on a first side of the first source/drain region. A front side source/drain contact is disposed on a second side of the first source/drain region that is opposite the first side, and a backside source/drain contact is disposed on the first side of the first source/drain region. The backside source/drain contact extends through the second dielectric layer.