Backside Contact Dielectric Liner to Prevent Nanosheet Gate Shorts
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Solution Overview
Problem
During the fabrication of semiconductor devices, particularly in backside processing, the removal/etching of spacer/insulator/dielectric layers can lead to shorts due to uncontrolled lateral etching, which is exacerbated during the silicide process, causing oxide loss and potential shorting of nanosheet devices.
Innovation Solution
A protective vertical dielectric liner is applied before the silicide process to prevent lateral etching of the backside interlayer dielectric layer, ensuring the integrity of the gate structure and preventing shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lateral etching is performed during silicide process to remove spacer/dielectric layers, then source/drain regions can be accessed and silicided, but uncontrolled lateral etching causes oxide loss and shorting of nanosheet devices
Solution Approach 1:
A dielectric liner is introduced as an intermediary protective layer between the lateral etching process and the gate dielectric layer. The liner selectively protects the gate dielectric from uncontrolled lateral etching while allowing the etching process to proceed in other regions, thus preventing oxide loss and device shorting without completely halting the silicide process
Solution Approach 2:
The dielectric liner is applied in advance before the lateral etching step to pre-establish protection against the harmful etching effect. This preliminary protective action counteracts the potential damage from uncontrolled lateral etching before it can occur, ensuring the gate dielectric integrity is maintained during the silicide process
2Adaptability or versatility
If dielectric layers are removed during backside processing to enable backside contacts, then interconnections can be established, but the gate structure becomes vulnerable to shorting
Solution Approach 1:
The dielectric liner serves as a protective intermediary that remains in place during backside processing steps. It allows backside contacts to be formed and interconnected while maintaining a protective barrier that prevents accidental shorting of the gate structure, thus enabling backside contact capability without compromising gate integrity
Data Source
AI summary
A microelectronic structure, comprising a nanosheet field-effect-transistor (FET) is provided that includes a source/drain and a backside contact connected to a backside surface of the source/drain. The backside contact has a first section having a first width as measured perpendicular to a gate direction. The backside contact also has a second section having a second width as measured perpendicular to the gate direction. The first width is smaller than the second width. A vertical dielectric liner is provided that includes a plurality of vertical segments. Each of the vertical segments are located adjacent to a sidewall of a first section of the backside contact. A backside interlayer dielectric layer is located adjacent to the vertical dielectric liner. The backside contact is in contact with the backside interlayer dielectric layer between the two vertical segments of the plurality vertical segments of the dielectric liner.