Backside Contact Structure for Scaled MOSFET Source/Drain Coupling
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Solution Overview
Problem
The scaling down of metal oxide semiconductor field effect transistors (MOSFETs) in semiconductor devices deteriorates their operating characteristics, leading to constraints on performance due to high integration, necessitating improvements in fabrication for enhanced electrical properties and reliability.
Innovation Solution
A semiconductor device is fabricated with a substrate, a lower power line buried in the substrate, a source/drain pattern, and a backside contact that penetrates the substrate, featuring an epitaxial pattern, a contact plug, and a metal-semiconductor compound layer, along with a dielectric substrate, an etch stop layer, and a gate electrode structure to enhance electrical coupling and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration density, then device integration is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent introduces a backside contact structure that penetrates through the substrate from the rear surface, adding a vertical dimension to the electrical connection pathway. This allows power lines to be accessed from the backside rather than requiring lateral routing, effectively utilizing the third dimension to resolve the conflict between integration density and operating characteristics by providing alternative current paths that reduce resistance without increasing lateral footprint.
Solution Approach 2:
The patent introduces a metal-semiconductor compound layer as an intermediary between the epitaxial contact and the power line. This intermediate layer facilitates better electrical coupling and reduces contact resistance, thereby improving operating characteristics while maintaining the scaled-down device dimensions required for high integration density.
2Ease of manufacture
If conventional contact structures are used in scaled devices, then fabrication is simpler, but contact resistance increases
Solution Approach 1:
The contact structure is segmented into multiple functional layers: an epitaxial contact region, a metal-semiconductor compound layer, and a power line. This segmentation allows each layer to be optimized for its specific function - the epitaxial region provides semiconductor compatibility, the compound layer provides low-resistance bonding, and the power line provides current conduction - thereby reducing overall contact resistance while maintaining fabrication feasibility through sequential deposition processes.
Solution Approach 2:
The patent employs a composite contact structure combining semiconductor material (epitaxial contact) with metal-semiconductor compound material. This composite approach leverages the advantages of both materials: the semiconductor material's compatibility with the device architecture and the metal compound's superior electrical conductivity, thereby achieving low contact resistance without sacrificing ease of manufacture.
3Ease of manufacture
If standard substrate structures are used, then manufacturing is easier, but leakage currents occur
Solution Approach 1:
The patent extracts the power line connection from the conventional lateral routing approach and relocates it to the backside of the substrate. By taking out the power line access point from the standard planar configuration and positioning it on the rear surface, the design eliminates leakage current paths that would otherwise exist through the substrate, while the backside contact process remains compatible with standard manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution improves the electrical properties and reliability of semiconductor devices by reducing contact resistance and preventing leakage currents, thereby enhancing performance and stability.
Implementation Method 1
a metal-semiconductor compound layer between the epitaxial pattern and the contact plug
Implementation Method 2
an etch stop layer on the dielectric substrate... The etch stop layer includes silicon doped with at least one of oxygen (O) and carbon (C)
Implementation Method 3
an epitaxial pattern coupled to a lower portion of the source/drain pattern
Data Source
AI summary
The present disclosure provides semiconductor devices including a field effect transistor (FET) and methods of fabricating the same. In some embodiments, a semiconductor device includes a substrate, a lower power line buried in a lower portion of the substrate, a source/drain pattern on the substrate, and a backside contact that penetrates the substrate and electrically couples the lower power line to the source/drain pattern. The backside contact includes an epitaxial pattern coupled to a lower portion of the source/drain pattern, a contact plug coupled to the lower power line, and a metal-semiconductor compound layer between the epitaxial pattern and the contact plug. The epitaxial pattern includes a top surface that protrudes toward the source/drain pattern.