Self-Aligned Backside Contact Layout for Low-Resistance Nanosheet FETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, the existing technologies face challenges in forming backside contacts for nanosheet FETs, particularly in achieving accurate alignment and reducing contact resistance while accommodating wafer distortion and non-uniformity, which affects the performance and reliability of nanosheet devices.
Innovation Solution
The solution involves forming a self-aligned sacrificial backside contact by creating a trench and epitaxial layers, allowing for the formation of a backside contact that is pre-defined, independent of backside lithography overlay performance, and enabling contacts to be formed with greater spacing and reduced need for upper contacts, thus improving alignment accuracy and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional backside contact formation is used, then alignment accuracy is affected by wafer distortion, but the contact area is limited
Solution Approach 1:
The patent performs preliminary actions by forming the bottom contact area through epitaxial growth and defining it with dielectric spacers before final contact formation. The dielectric spacer is formed to overlap the bottom isolation region, pre-defining the contact boundaries and protecting against misalignment during subsequent processing steps
Solution Approach 2:
The patent extends the contact area by utilizing the vertical dimension and lateral overlap with the isolation region. The dielectric spacer overlaps both the vertical side surface and lower horizontal surface of the bottom isolation region, creating a three-dimensional contact structure that increases effective contact area without compromising alignment
2Manufacturing precision
If contact spacing is increased, then alignment difficulty is reduced, but upper contacts become insufficient
Solution Approach 1:
The patent segments the contact structure into distinct bottom and upper contacts with different functions. The bottom contact provides primary electrical connection with larger area, while upper contacts provide secondary connection, allowing greater spacing between them while maintaining sufficient overall contact capability
Solution Approach 2:
The dielectric spacer acts as an intermediary element that defines and protects the bottom contact area. It overlaps the bottom isolation region and provides a reference structure that facilitates accurate contact formation while allowing increased spacing between contacts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility and accuracy of source drain contact formation, reduces contact resistance, and improves the overall performance and reliability of nanosheet FETs by allowing for both top and bottom contact formation with improved alignment and reduced wafer distortion issues.
Implementation Method 1
a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact
Implementation Method 2
forming a shallow trench isolation in the divided double nanosheet stack, forming an undoped silicon buffer epitaxy
Data Source
AI summary
A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.


