Backside Contact Layout Using Overlay Keys for Dense Multi-Gate Chips
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in reducing capacitance and ensuring electrical stability as pitch sizes decrease, particularly in forming reliable contacts and wiring structures for multi-gate transistors with complex three-dimensional channel configurations.
Innovation Solution
The method involves forming a substrate with specific trench and overlay key structures, including first and second trenches with varying widths, and using overlay keys to create active patterns and contacts, allowing for the formation of source/drain and gate electrodes, as well as backside contacts and wiring lines that penetrate through the substrate to improve contact reliability and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size is reduced to increase device density, then device density is improved, but capacitance increases and electrical stability deteriorates
Solution Approach 1:
The patent transitions from planar contacts to three-dimensional vertical contacts that penetrate through the substrate thickness direction. This dimensional change allows contacts to be formed at different depths (first contact at first surface level, second contact at second surface level), reducing capacitive coupling between adjacent contacts while maintaining high device density through vertical stacking.
Solution Approach 2:
The contact structure is segmented into multiple levels: first contacts formed at the first surface level, second contacts formed at the second surface level after substrate thinning, and intermediate overlay keys at different heights. This segmentation separates the electrical pathways, reducing parasitic capacitance between adjacent contacts while enabling higher pitch density.
2Reliability
If multi-gate transistor with three-dimensional channel is formed, then current control capability is improved, but device fabrication complexity increases
Solution Approach 1:
Overlay keys are formed in advance at specific positions and heights within the substrate before the multi-gate transistor fabrication process. These pre-formed keys serve as alignment references and structural templates, simplifying subsequent steps of forming active patterns, source/drain regions, and gate electrodes with precise three-dimensional configurations.
Solution Approach 2:
The overlay keys act as intermediary structures that mediate between the substrate and the multi-gate transistor components. They provide physical references for alignment and structural guidance for forming complex three-dimensional channels, reducing the overall fabrication complexity by breaking down the complex process into manageable steps with clear reference points.
3Reliability
If backside contact is formed by removing substrate portion, then contact reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Overlay keys are formed in advance at predetermined positions and heights within the substrate before backside contact formation. These pre-formed keys serve as alignment references, allowing precise positioning of the mask layer and subsequent contact holes without requiring extremely high precision substrate removal. The keys are created at specific heights to provide unambiguous reference points for alignment.
Data Source
AI summary
The present disclosure relates to semiconductor device fabricating methods. An example semiconductor device fabricating method comprises forming a substrate including a chip area and an outside chip area and having a first surface and a second surface opposite to the first surface, forming a first trench, having a first width on the first surface, in the outside chip area of the substrate, forming a second trench, having a second width smaller than the first width, within the first trench, forming a first overlay key filling the first trench and the second trench, forming an active pattern on the first surface of the substrate, forming a source/drain pattern and a gate electrode on the active pattern in the chip area, and forming a backside contact on the second surface using a bottom surface of the first overlay key in the second trench.